公开(公告)号：US09331218B2

公开(公告)日：2016-05-03

申请号：US13614815

申请日：2012-09-13

申请人： Woo-Seok Cheong ,  Rae-Man Park

发明人： Woo-Seok Cheong ,  Rae-Man Park

IPC分类号： H01L21/00 ,  H01L31/0224 ,  H01L31/0749 ,  H01L31/046 ,  H01L31/0465

CPC分类号： H01L31/022466 ,  H01L31/022483 ,  H01L31/046 ,  H01L31/0465 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

摘要： Provided are a solar cell module and a method of manufacturing the same. The solar cell module including: a substrate; a bottom electrode layer discontinuously formed on the substrate; a light absorbing layer formed on the bottom electrode layer and including a first trench that exposes the bottom electrode layer; and a transparent electrode layer extending from the top of the light absorbing layer to the bottom electrode layer at the bottom of the first trench, and including a first oxide layer, a metal layer, and a second oxide layer, all of which are staked on the light absorbing layer and the bottom electrode layer.

摘要翻译： 提供一种太阳能电池模块及其制造方法。 太阳能电池模块包括：基板; 在基板上不连续地形成的底部电极层; 形成在所述底部电极层上并包括暴露所述底部电极层的第一沟槽的光吸收层; 以及透明电极层，其从所述光吸收层的顶部延伸到所述第一沟槽的底部的所述底部电极层，并且包括第一氧化物层，金属层和第二氧化物层，所述第一氧化物层， 光吸收层和底电极层。

公开(公告)号：US08572546B2

公开(公告)日：2013-10-29

申请号：US13371487

申请日：2012-02-13

申请人： Jaeheon Shin ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

发明人： Jaeheon Shin ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.

摘要翻译： 提供了对晶体管进行建模的方法。 该方法包括以下步骤：（a）使用参考栅极电压，参考漏极电流和参考漏极电压提取包括栅电极，源区和漏区的晶体管的沟道层的参考迁移率值，（b ）将包括模型参数的移动性函数拟合在参考迁移率值上以提取模型参数，以及（c）将所提取的模型参数放入漏极电流建模函数中以计算流过漏极区域和漏极区域之间的沟道层的漏极电流 源极区域由施加到栅极电极的任意栅极电压和施加到漏极区域的任意漏极电压限定的偏置状态。 还提供了相关装置。

公开(公告)号：US20120297351A1

公开(公告)日：2012-11-22

申请号：US13371487

申请日：2012-02-13

申请人： Jaeheon SHIN ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

发明人： Jaeheon SHIN ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.

摘要翻译： 提供了对晶体管进行建模的方法。 该方法包括以下步骤：（a）使用参考栅极电压，参考漏极电流和参考漏极电压提取包括栅电极，源区和漏区的晶体管的沟道层的参考迁移率值，（b ）将包括模型参数的移动性函数拟合在参考迁移率值上以提取模型参数，以及（c）将所提取的模型参数放入漏极电流建模函数中以计算流过漏极区域和漏极区域之间的沟道层的漏极电流 源极区域由施加到栅极电极的任意栅极电压和施加到漏极区域的任意漏极电压限定的偏置状态。 还提供了相关装置。

公开(公告)号：US06693294B1

公开(公告)日：2004-02-17

申请号：US10331945

申请日：2002-12-31

申请人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

发明人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

IPC分类号： H01L3900

CPC分类号： H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

摘要： Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

摘要翻译： 提供了一种肖特基势垒隧道晶体管（SBTT）及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅（SOI）层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧，源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。 在SBTT中，SOI层形成为超薄的厚度，以最小化泄漏电流的发生，栅极下方的SOI层中的沟道被栅极和导电层完全包围，从而提高了操作特性 的SBTT。

公开(公告)号：US09019219B2

公开(公告)日：2015-04-28

申请号：US13546519

申请日：2012-07-11

申请人： Woo-Seok Cheong ,  Jaeheon Shin

发明人： Woo-Seok Cheong ,  Jaeheon Shin

IPC分类号： G06F3/041 ,  G06F3/044

CPC分类号： G06F3/044 ,  G06F2203/04103

摘要： Touch screen panels are provided. The touch screen panel may include a first hybrid electrode including first electrode cells arranged on a substrate in a first direction and first connection electrodes connecting the first electrode cells to each other in the first direction, and a second hybrid electrode spaced apart from the first hybrid electrode on the substrate. The second hybrid electrode may include second electrode cells arranged in a second direction crossing the first direction and second connection electrodes connecting the second electrode cells to each other in the second direction. The second electrode cells are disposed between the first connection electrodes. The first hybrid electrode may include a first lower transparent layer and a first metal layer which are sequentially stacked, and the second hybrid electrode may include a second lower transparent layer and a second metal layer which are sequentially stacked.

摘要翻译： 提供触摸屏面板。 触摸屏面板可以包括第一混合电极，第一混合电极包括在第一方向上布置在基板上的第一电极单元和在第一方向上将第一电极单元彼此连接的第一连接电极和与第一混合物间隔开的第二混合电极 电极。 第二混合电极可以包括沿与第一方向交叉的第二方向布置的第二电极单元和在第二方向上将第二电极单元彼此连接的第二连接电极。 第二电极单元设置在第一连接电极之间。 第一混合电极可以包括依次层叠的第一下透明层和第一金属层，第二混合电极可以包括依次层叠的第二下透明层和第二金属层。

公开(公告)号：US20120298985A1

公开(公告)日：2012-11-29

申请号：US13475366

申请日：2012-05-18

申请人： Sung Mook CHUNG ,  Woo-Seok Cheong ,  Jaeheon Shin ,  Chan Hwa Hong

发明人： Sung Mook CHUNG ,  Woo-Seok Cheong ,  Jaeheon Shin ,  Chan Hwa Hong

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78693

摘要： Provided are a thin film transistor able to increase or maximize productivity and production yield, and a method of fabricating the same. The method of fabricating the thin film transistor includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an active layer formed of an amorphous oxide semiconductor on the gate insulating layer, and respectively forming a source electrode and a drain electrode on both sides of the active layer above the gate electrode. The amorphous oxide semiconductor of the active layer may be doped with a metal oxide dielectric.

摘要翻译： 提供能够增加或最大化生产率和生产率的薄膜晶体管及其制造方法。 制造薄膜晶体管的方法包括：在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成由非晶氧化物半导体形成的有源层，分别形成源电极和 位于栅电极上方的有源层的两侧的漏电极。 有源层的无定形氧化物半导体可以掺杂有金属氧化物电介质。

公开(公告)号：US20060048706A1

公开(公告)日：2006-03-09

申请号：US10527056

申请日：2002-12-30

申请人： Woo-Seok Cheong ,  Seong-Jae Lee ,  Won-Ju Jo ,  Moon-Gyu Jang

发明人： Woo-Seok Cheong ,  Seong-Jae Lee ,  Won-Ju Jo ,  Moon-Gyu Jang

IPC分类号： C23C16/00

CPC分类号： H01L21/67207 ,  H01L29/66848

摘要： In a process for manufacturing a hyperfine semiconductor device, an apparatus for manufacturing a semiconductor device such as a schottky barrier MOSFET and a method for manufacturing the semiconductor device using the same are provided. Two chambers are connected with each other. A cleaning process, a metal layer forming process, and subsequent processes can be performed in situ by using the two chambers, thereby the attachment of the unnecessary impurities and the formation of the oxide can be prevented and the optimization of the process can be accomplished.

摘要翻译： 在制造超精细半导体器件的方法中，提供了用于制造诸如肖特基势垒MOSFET的半导体器件的装置以及使用其制造半导体器件的方法。 两个腔室相互连接。 可以通过使用两个室来原位进行清洁处理，金属层形成工艺和随后的工艺，从而可以防止不必要的杂质的附着和氧化物的形成，并且可以实现工艺的优化。

公开(公告)号：US09115425B2

公开(公告)日：2015-08-25

申请号：US13182590

申请日：2011-07-14

申请人： Woo-Seok Cheong

发明人： Woo-Seok Cheong

IPC分类号： C23C16/44 ,  B25J18/00 ,  B25J15/06 ,  C23C16/458 ,  H01L21/677 ,  C23C14/34 ,  C23C14/56 ,  H01L21/67

CPC分类号： C23C16/4587 ,  C23C14/34 ,  C23C14/568 ,  H01L21/67173 ,  H01L21/67712 ,  H01L21/67718 ,  H01L21/67751 ,  H01L21/6776

摘要： Provided is a thin film depositing apparatus. The thin film depositing apparatus includes: a loading chamber loading a plurality of substrates; a first process chamber connected to the loading chamber and including a plurality of sputter guns inducing a first plasma on the plurality of substrates; a buffer chamber connected to the other side of the first process chamber facing the loading chamber; and a substrate transfer module simultaneously passing the plurality of substrates between the plurality of sputter guns during a process using the first plasma and transferring the plurality of substrates from the first process chamber to the buffer chamber.

摘要翻译： 提供了一种薄膜沉积设备。 薄膜沉积设备包括：装载多个基板的装载室; 连接到所述装载室并包括多个溅射枪的第一处理室，所述多个溅射枪在所述多个基板上引入第一等离子体; 连接到所述第一处理室的面向所述装载室的另一侧的缓冲室; 以及基板转移模块，在使用第一等离子体的工艺中将多个基板同时通过多个溅射枪之间并将多个基板从第一处理室传送到缓冲室。

公开(公告)号：US20130016054A1

公开(公告)日：2013-01-17

申请号：US13546519

申请日：2012-07-11

申请人： Woo-Seok Cheong ,  Jaeheon Shin

发明人： Woo-Seok Cheong ,  Jaeheon Shin

IPC分类号： G06F3/041

CPC分类号： G06F3/044 ,  G06F2203/04103

摘要： Touch screen panels are provided. The touch screen panel may include a first hybrid electrode including first electrode cells arranged on a substrate in a first direction and first connection electrodes connecting the first electrode cells to each other in the first direction, and a second hybrid electrode spaced apart from the first hybrid electrode on the substrate. The second hybrid electrode may include second electrode cells arranged in a second direction crossing the first direction and second connection electrodes connecting the second electrode cells to each other in the second direction. The second electrode cells are disposed between the first connection electrodes. The first hybrid electrode may include a first lower transparent layer and a first metal layer which are sequentially stacked, and the second hybrid electrode may include a second lower transparent layer and a second metal layer which are sequentially stacked.

摘要翻译： 提供触摸屏面板。 触摸屏面板可以包括第一混合电极，第一混合电极包括在第一方向上布置在基板上的第一电极单元和在第一方向上将第一电极单元彼此连接的第一连接电极和与第一混合物间隔开的第二混合电极 电极。 第二混合电极可以包括沿与第一方向交叉的第二方向布置的第二电极单元和在第二方向上将第二电极单元彼此连接的第二连接电极。 第二电极单元设置在第一连接电极之间。 第一混合电极可以包括依次层叠的第一下透明层和第一金属层，第二混合电极可以包括依次层叠的第二下透明层和第二金属层。

公开(公告)号：US20110147735A1

公开(公告)日：2011-06-23

申请号：US12871448

申请日：2010-08-30

申请人： Woo-Seok Cheong

发明人： Woo-Seok Cheong

IPC分类号： H01L29/22 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/4908 ,  H01L29/78696

摘要： Provided are a thin film transistor and a method of forming the same. The thin film transistor includes: a substrate; a source electrode and a drain electrode on the substrate; an oxide active layer between the source electrode and the drain electrode; a gate electrode on one side of the oxide active layer; a gate dielectric layer between the gate electrode and the oxide active layer; and a buffer layer between the gate dielectric layer and the oxide active layer.

摘要翻译： 提供一种薄膜晶体管及其形成方法。 薄膜晶体管包括：基板; 源电极和漏电极; 源电极和漏电极之间的氧化物活性层; 氧化物活性层一侧的栅电极; 栅电极和氧化物活性层之间的栅介质层; 以及在栅介电层和氧化物活性层之间的缓冲层。