公开(公告)号：US06693294B1

公开(公告)日：2004-02-17

申请号：US10331945

申请日：2002-12-31

申请人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

发明人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

IPC分类号： H01L3900

CPC分类号： H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

摘要： Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

摘要翻译： 提供了一种肖特基势垒隧道晶体管（SBTT）及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅（SOI）层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧，源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。 在SBTT中，SOI层形成为超薄的厚度，以最小化泄漏电流的发生，栅极下方的SOI层中的沟道被栅极和导电层完全包围，从而提高了操作特性 的SBTT。

公开(公告)号：US06723587B2

公开(公告)日：2004-04-20

申请号：US10331568

申请日：2002-12-31

申请人： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

发明人： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

IPC分类号： H01L2184

CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78609

摘要： An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.

摘要翻译： 提供了具有高积分密度，低功耗但高性能的超小尺寸SOI MOSFET及其制造方法。 该方法包括制备在其上形成单晶硅层的SOI衬底，在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层，形成开口，以暴露单晶硅层，刻蚀至少部分 第一介电材料层，形成将由第二导电类型杂质注入由开口露出的单晶硅层的沟道区，在单晶硅层中形成源极区和漏极区，使用热量扩散第一介电材料层的杂质 在沟道区域的开口中形成栅极电介质层，在栅极电介质层上形成栅电极以配合在开口中，在栅极电极的SOI衬底的整个表面上形成第二电介质层 形成，形成接触孔以露出栅电极，源极区和漏极 区域蚀刻第二介电材料层的部分，以及形成用于埋入接触孔的金属互连。

公开(公告)号：US5872372A

公开(公告)日：1999-02-16

申请号：US712410

申请日：1996-09-11

申请人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

发明人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

IPC分类号： H01L41/107 ,  H01L29/786 ,  H01L29/84 ,  H01L41/08 ,  H01L29/82

CPC分类号： H01L29/7849 ,  H01L29/84 ,  H01L29/78 ,  H01L29/786

摘要： A thin film transistor is disclosed comprising a piezoelectric film formed on a piezoresistive body of an ultra thin film and a gate electrode formed on the piezoelectric film. Due to the force generated from the piezoelectric film by an electric field generated according to the strength of a voltage applied to the gate electrode, a pressure is applied on the piezoresistive body to vary the resistance of the piezoresistive body. Thus, the quantity of current that flows from a source terminal through the piezoresistive channel to a drain terminal can be controlled. Since the piezoresistive body can be formed on a plane, a thin film transistor with a three-dimensional structure can be manufactured.

摘要翻译： 公开了一种薄膜晶体管，其包括形成在超薄膜的压阻体上的压电膜和形成在压电膜上的栅电极。 由于通过根据施加到栅电极的电压的强度而产生的电场由压电膜产生的力，对压阻体施加压力以改变压阻体的电阻。 因此，可以控制从源极端子通过压阻通道流向漏极端子的电流量。 由于可以在平面上形成压阻体，因此可以制造具有三维结构的薄膜晶体管。

公开(公告)号：US5883419A

公开(公告)日：1999-03-16

申请号：US850013

申请日：1997-05-01

申请人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

发明人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

IPC分类号： H01L41/00 ,  H01L45/00 ,  B02J17/40 ,  B05D3/06

CPC分类号： H01L45/00

摘要： A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.

摘要翻译： 根据本发明的晶体管包括用作电子流的通道的超薄Mo-C膜，其中薄金属膜的两端分别用作晶体管的源极和漏极端子; 形成在Mo-C膜上的压电膜，用于根据由栅极电压提供的施加的电场产生力; 以及形成在作为施加栅极电压的晶体管的栅极的压电膜上产生施加的电场的电极膜; 并且其中源极和漏极端子之间的Mo-C膜的电阻根据施加的栅极电压产生的力而改变。 该晶体管可以用作具有层叠结构的三维集成电路的元件。

公开(公告)号：US5760675A

公开(公告)日：1998-06-02

申请号：US716550

申请日：1996-09-19

申请人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

发明人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

IPC分类号： G01L1/18 ,  G01L1/22 ,  H01L29/84 ,  H01L41/00

CPC分类号： G01L1/2293

摘要： Disclosed is the method of producing a piezo-device utilizing an ultra-thin Mo-C film as a piezoresistive material for a general class of improved piezo-device with the high sensitivity and the weak temperature dependence.

摘要翻译： 公开了利用超薄Mo-C膜作为压敏电阻材料的压电器件的制造方法，该压电器件具有高灵敏度和弱温度依赖性的一类改进的压电器件。

公开(公告)号：US5880484A

公开(公告)日：1999-03-09

申请号：US706238

申请日：1996-09-04

申请人： Kyoung-Wan Park ,  Seong-Jae Lee ,  Min-Cheol Shin

发明人： Kyoung-Wan Park ,  Seong-Jae Lee ,  Min-Cheol Shin

IPC分类号： H01L29/68 ,  H01L21/334 ,  H01L29/06 ,  H01L29/12 ,  H01L29/205 ,  H01L29/66 ,  H01L29/772 ,  H01L29/778 ,  H01L29/80

CPC分类号： B82Y10/00 ,  H01L29/127 ,  H01L29/66939 ,  H01L29/772 ,  H01L29/7786

摘要： A lateral resonant tunneling transistor having two non-symmetric quantum dots is disclosed. When a negative voltage is supplied to each plurality of thin split gates, two non-symmetric quantum dots are formed owing to the formation of the potential barrier. Thus when a forward bias voltage is applied, the resonant tunneling phenomena occur twice successively. Through these two successive resonant tunneling phenomena and by lowering the height of the third potential barrier 6a, the resonant tunneling current can be maximized.

摘要翻译： 公开了具有两个非对称量子点的横向谐振隧穿晶体管。 当向每个多个薄分割栅极提供负电压时，由于形成势垒而形成两个非对称量子点。 因此，当施加正向偏置电压时，谐振隧道现象连续发生两次。 通过这两个连续的谐振隧道现象，并且通过降低第三势垒6a的高度，可以使谐振隧穿电流最大化。

公开(公告)号：US5519232A

公开(公告)日：1996-05-21

申请号：US352046

申请日：1994-11-30

申请人： Kyoung-Wan Park ,  Seong-Jae Lee ,  Min-Cheol Shin

发明人： Kyoung-Wan Park ,  Seong-Jae Lee ,  Min-Cheol Shin

IPC分类号： H01L29/68 ,  H01L21/338 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： B82Y10/00 ,  H01L29/66977

摘要： A quantum interference device comprises a semi-insulating GaAs substrate; GaAs and AlGaAs layers sequentially formed with high purity on the substrate; a two-dimensional electron gas layer formed in the GaAs layer and serving as a channel; source/drain regions formed on the semi-insulating GaAs substrate and at both ends of a laminated portion composed of the GaAs/AlGaAs layers; and a gate formed on the AlGaAs layer and having a periodic structure wherein the length thereof varies in a periodic manner in a transverse direction. In the device, the electron gas layer formed in the GaAs layer is used as an electron path, and the phases of electrons passing along different electron paths are caused to interfere with each other by the gate, thereby causing the current of a drain therein to be maximized or minimized. The transconductance can be significantly increased.

摘要翻译： 量子干涉装置包括半绝缘GaAs衬底; 在衬底上依次形成高纯度的GaAs和AlGaAs层; 形成在GaAs层中并用作沟道的二维电子气层; 在半绝缘GaAs衬底上形成的源极/漏极区域和由GaAs / AlGaAs层构成的层叠部分的两端; 以及形成在AlGaAs层上并且具有周期性结构的栅极，其中其长度在横向上以周期性方式变化。 在该器件中，使用形成在GaAs层中的电子气层作为电子通路，使通过不同的电子路径的电子相被栅极相互干扰，从而使其中的漏极的电流 最大化或最小化。 跨导可以显着增加。

公开(公告)号：US06489587B2

公开(公告)日：2002-12-03

申请号：US09752671

申请日：2000-12-28

申请人： Jeong-Sook Ha ,  Kyoung-Wan Park ,  Seung-Min Park ,  Young-Jo Ko

发明人： Jeong-Sook Ha ,  Kyoung-Wan Park ,  Seung-Min Park ,  Young-Jo Ko

IPC分类号： B23K2600

CPC分类号： C23C14/0652 ,  C23C14/28 ,  C30B23/002 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02581 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/167

摘要： An apparatus for fabricating silicon thin films for use in laser ablation includes a silicon substrate rotatably mounted in a process chamber maintaining a ultra high vacuum, pulsed light source means mounted outside the process chamber for emitting a pulsed light beam, target rotating means mounted in the process chamber for rotating a plurality of targets mounted therein, the targets being made of a different material, light beam splitting means for splitting the pulsed light beam into double light beams of the same intensity, light beam intensity regulating means for regulating the intensity of the double light beams, wherein the targets are mounted to face the silicon substrate so as to uniformly overlap the vaporization products of the targets generated by irradiating the double light bears on the silicon substrate.

摘要翻译： 用于制造用于激光烧蚀的硅薄膜的装置包括可旋转地安装在保持超高真空的处理室中的硅衬底，安装在处理室外部用于发射脉冲光束的脉冲光源装置，安装在 处理室，用于旋转安装在其中的多个目标，所述目标由不同的材料制成;光束分离装置，用于将脉冲光束分成具有相同强度的双光束;光束强度调节装置，用于调节 双光束，其中靶被安装成面对硅衬底，以便均匀地重叠通过在硅衬底上照射双光轴产生的靶的汽化产物。

公开(公告)号：US06242326B1

公开(公告)日：2001-06-05

申请号：US09452853

申请日：1999-12-02

申请人： Jung-Rae Ro ,  Sung-Bock Kim ,  Kyoung-Wan Park

发明人： Jung-Rae Ro ,  Sung-Bock Kim ,  Kyoung-Wan Park

IPC分类号： H01L21203

CPC分类号： B82Y10/00 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02614 ,  H01L29/127 ,  Y10S438/962

摘要： A method for fabricating a compound semiconductor substrate having a quantum dot array structure includes the steps of forming a plurality of dielectric thin layer patterns on a substrate, thereby forming an exposed area of the substrate, sequentially forming buffer layers and barrier layers in a pyramid shape on the exposed area of the substrate, forming Ga droplets on the barrier layers, transforming the Ga droplets into GaAs quantum dots, performing a thermal process to the substrate, and growing the buffer layers and the barrier layers to thereby form a passivation layer capping the GaAs quantum dots.

摘要翻译： 一种制造具有量子点阵列结构的化合物半导体衬底的方法包括以下步骤：在衬底上形成多个电介质薄层图案，从而形成衬底的暴露区域，依次形成金字塔形状的缓冲层和阻挡层 在衬底的暴露区域上，在阻挡层上形成Ga液滴，将Ga液滴转变成GaAs量子点，对衬底进行热处理，并使缓冲层和阻挡层生长，从而形成钝化层 GaAs量子点。