公开(公告)号：US08601680B2

公开(公告)日：2013-12-10

申请号：US12545371

申请日：2009-08-21

申请人： Woo-suk Choi ,  Deok-heung Kim

发明人： Woo-suk Choi ,  Deok-heung Kim

IPC分类号： H05K3/00 ,  H05K3/20

CPC分类号： H05K3/0085 ,  B65H18/103 ,  B65H23/188 ,  B65H2301/522 ,  B65H2701/1752 ,  H05K1/0393 ,  H05K3/0097 ,  H05K2201/10204 ,  H05K2203/1545

摘要： Provided is a method of roll-to-roll processing of semiconductor parts, the method including: supplying to a processing unit a first material uncoiled from a first roll for processing at the processing unit; connecting a leading board to a leading portion of the first material before the processing so that the first material led by the leading board is processed during transfer in the processing unit along a path; cutting the leading board from the leading portion of the first material after the processing; and if a terminal edge of the first material begins to be processed at the processing unit, connecting another leading board to a leading portion of a second material uncoiled from a second roll and supplying the second material to the processing unit for processing.

摘要翻译： 提供一种半导体部件的卷对卷处理的方法，该方法包括：向处理单元提供从第一辊展开的第一材料，以在处理单元处进行处理; 在处理之前将前导板连接到第一材料的引导部分，使得由前导板引导的第一材料沿着路径在处理单元中传送期间被处理; 在处理后从第一材料的引导部分切割引导板; 并且如果所述第一材料的端边缘在所述处理单元处开始被处理，则将另一前导板连接到从第二辊展开的第二材料的引导部分，并将所述第二材料供应到所述处理单元用于处理。

公开(公告)号：US07541664B2

公开(公告)日：2009-06-02

申请号：US11134138

申请日：2005-05-20

申请人： Soo-bong Lee ,  Jung-Do Kim ,  Woo-suk Choi ,  Eun-hee Kim

发明人： Soo-bong Lee ,  Jung-Do Kim ,  Woo-suk Choi ,  Eun-hee Kim

IPC分类号： H01L23/495

CPC分类号： H01L24/85 ,  H01L23/4951 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Provided is a lead frame having an improved wire bonding property of inner leads and an improved soldering property of outer leads and preventing defects with high producing yield, and a method of manufacturing the lead frame. The lead frame includes a plurality of inner leads formed with predetermined intervals between them; and a plurality of outer leads extended from the inner leads in length directions of the inner leads, each of which has an end portion overlapped with the inner lead and coupled thereto and the other end connected to neighboring outer lead by a supporting portion.

摘要翻译： 提供一种引线框架，其具有改善的内引线的引线接合性能和改善的外引线的焊接性能，并且防止产率高的缺陷，以及制造引线框架的方法。 引线框架包括在它们之间以预定间隔形成的多个内引线; 以及从所述内引线在所述内引线的长度方向上延伸的多个外引线，所述多个外引线具有与所述内引线重叠并与其连接的端部，并且另一端通过支撑部连接到相邻的外引线。

公开(公告)号：US20080169999A1

公开(公告)日：2008-07-17

申请号：US11881874

申请日：2007-07-30

申请人： Eun-hee Kim ,  Woo-suk Choi ,  Jin-woo Lee

发明人： Eun-hee Kim ,  Woo-suk Choi ,  Jin-woo Lee

IPC分类号： G09G3/28

CPC分类号： H01J11/24 ,  H01J9/241 ,  H01J9/242 ,  H01J11/16 ,  H01J11/36 ,  H01J11/38 ,  H01J2211/245

摘要： A dielectric layer of a plasma display panel that can coat a discharge electrode regardless of the form of the discharge electrode and that can be manufactured using a low temperature process, a method of forming the dielectric layer, and a plasma display panel including the dielectric layer. Thus the dielectric layer includes an organic material and is manufactured using an electro-deposition coating method.

摘要翻译： 等离子体显示面板的电介质层，其能够涂覆放电电极，而不管放电电极的形式如何，并且可以使用低温工艺制造，形成电介质层的方法以及包括电介质层的等离子体显示面板 。 因此，电介质层包括有机材料，并且使用电沉积涂布法制造。

公开(公告)号：US20060071310A1

公开(公告)日：2006-04-06

申请号：US11194872

申请日：2005-08-01

申请人： Woo-suk Choi ,  Joong-do Kim ,  Eun-hee Kim ,  Soo-bong Lee

发明人： Woo-suk Choi ,  Joong-do Kim ,  Eun-hee Kim ,  Soo-bong Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/85439 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/15738 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/01082 ,  H01L2924/00

摘要： Provided are a semiconductor lead frame, a semiconductor package having the semiconductor lead frame, and a method of plating the semiconductor lead frame. The method includes preparing a substrate formed of a Fe—Ni alloy (alloy 42), and a plating layer that contains grains less than 1 micrometer in size and is plated on the substrate. The growth of whiskers when a Sn plated layer is formed on a substrate formed of a Fe—Ni alloy (alloy 42) can be suppressed by minimizing the grain size of the Sn plated layer.

公开(公告)号：US07815481B2

公开(公告)日：2010-10-19

申请号：US11706706

申请日：2007-02-13

申请人： Woo-suk Choi ,  Eun-hee Kim

发明人： Woo-suk Choi ,  Eun-hee Kim

IPC分类号： H01J9/02 ,  H01J9/00 ,  H01J17/49

CPC分类号： H01J9/02 ,  H01J11/16 ,  H01J11/36 ,  H01J11/38 ,  H01J2211/366

摘要： A plasma display panel, a method of manufacturing an electrode burying dielectric wall of a plasma display panel, and a method of manufacturing an electrode burying dielectric wall of the plasma display panel. The plasma display panel comprises a front substrate, a rear substrate separated from the front substrate in a vertical direction, front discharge electrodes and rear discharge electrodes disposed between the front substrate separated from one another by an insulating layer, a high dielectric layer surrounding the front discharge electrodes and the rear discharge electrodes, discharge cells, at least a portion of each discharge cell being surrounded by the high dielectric layer, a phosphor layer disposed in each of the discharge cells, and a discharge gas filled in the discharge cells.

摘要翻译： 等离子体显示面板，等离子体显示面板的埋入电介质电极的电极的制造方法以及等离子体显示面板的埋置电介质壁的电极的制造方法。 等离子体显示面板包括前基板，在垂直方向与前基板分离的后基板，前放电电极和设置在通过绝缘层彼此分离的前基板之间的后放电电极，围绕前端的高介电层 放电电极和后放电电极，放电单元，每个放电单元的至少一部分被高电介质层包围，设置在每个放电单元中的荧光体层和填充在放电单元中的放电气体。

公开(公告)号：US07501692B2

公开(公告)日：2009-03-10

申请号：US11194872

申请日：2005-08-01

申请人： Woo-suk Choi ,  Joong-do Kim ,  Eun-hee Kim ,  Soo-bong Lee

发明人： Woo-suk Choi ,  Joong-do Kim ,  Eun-hee Kim ,  Soo-bong Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/85439 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/15738 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/01082 ,  H01L2924/00

摘要： Provided are a semiconductor lead frame, a semiconductor package having the semiconductor lead frame, and a method of plating the semiconductor lead frame. The method includes preparing a substrate formed of a Fe—Ni alloy (alloy 42), and a plating layer that contains grains less than 1 micrometer in size and is plated on the substrate. The growth of whiskers when a Sn plated layer is formed on a substrate formed of a Fe—Ni alloy (alloy 42) can be suppressed by minimizing the grain size of the Sn plated layer.

摘要翻译： 提供一种半导体引线框架，具有半导体引线框架的半导体封装以及对该半导体引线框架进行电镀的方法。 该方法包括制备由Fe-Ni合金（合金42）形成的基板和包含小于1微米的晶粒并镀在基板上的镀层。 在由Fe-Ni合金（合金42）形成的基板上形成Sn镀层的晶须的生长可以通过使镀Sn层的晶粒尺寸最小化来抑制晶须的生长。

公开(公告)号：US20070200500A1

公开(公告)日：2007-08-30

申请号：US11706706

申请日：2007-02-13

申请人： Woo-suk Choi ,  Eun-hee Kim

发明人： Woo-suk Choi ,  Eun-hee Kim

IPC分类号： H01J17/49 ,  C23C14/04

CPC分类号： H01J9/02 ,  H01J11/16 ,  H01J11/36 ,  H01J11/38 ,  H01J2211/366

摘要： A plasma display panel, a method of manufacturing an electrode burying dielectric wall of a plasma display panel, and a method of manufacturing an electrode burying dielectric wall of the plasma display panel. The plasma display panel comprises a front substrate, a rear substrate separated from the front substrate in a vertical direction, front discharge electrodes and rear discharge electrodes disposed between the front substrate separated from one another by an insulating layer, a high dielectric layer surrounding the front discharge electrodes and the rear discharge electrodes, discharge cells, at least a portion of each discharge cell being surrounded by the high dielectric layer, a phosphor layer disposed in each of the discharge cells, and a discharge gas filled in the discharge cells.

摘要翻译： 等离子体显示面板，等离子体显示面板的埋入电介质电极的电极的制造方法以及等离子体显示面板的埋置电介质壁的电极的制造方法。 等离子体显示面板包括前基板，在垂直方向与前基板分离的后基板，前放电电极和设置在通过绝缘层彼此分离的前基板之间的后放电电极，围绕前端的高介电层 放电电极和后放电电极，放电单元，每个放电单元的至少一部分被高电介质层包围，设置在每个放电单元中的荧光体层和填充在放电单元中的放电气体。

公开(公告)号：US20060049493A1

公开(公告)日：2006-03-09

申请号：US11134138

申请日：2005-05-20

申请人： Soo-bong Lee ,  Jung-Do Kim ,  Woo-suk Choi ,  Eun-hee Kim

发明人： Soo-bong Lee ,  Jung-Do Kim ,  Woo-suk Choi ,  Eun-hee Kim

IPC分类号： H01L23/495

CPC分类号： H01L24/85 ,  H01L23/4951 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Provided is a lead frame having an improved wire bonding property of inner leads and an improved soldering property of outer leads and preventing defects with high producing yield, and a method of manufacturing the lead frame. The lead frame includes a plurality of inner leads formed with predetermined intervals between them; and a plurality of outer leads extended from the inner leads in length directions of the inner leads, each of which has an end portion overlapped with the inner lead and coupled thereto and the other end connected to neighboring outer lead by a supporting portion.

摘要翻译： 提供一种引线框架，其具有改善的内引线的引线接合性能和改善的外引线的焊接性能，并且防止产率高的缺陷，以及制造引线框架的方法。 引线框架包括在它们之间以预定间隔形成的多个内引线; 以及从所述内引线在所述内引线的长度方向上延伸的多个外引线，所述多个外引线具有与所述内引线重叠并与其连接的端部，并且另一端通过支撑部连接到相邻的外引线。