公开(公告)号：US20070268749A1

公开(公告)日：2007-11-22

申请号：US11802282

申请日：2007-05-22

申请人： Dae-Mann Kim ,  Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Sang-Pil Sim

发明人： Dae-Mann Kim ,  Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Sang-Pil Sim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3409 ,  G11C16/345

摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.

摘要翻译： 公开了一种操作非易失性存储器件的方法。 存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。 该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

公开(公告)号：US20070105309A1

公开(公告)日：2007-05-10

申请号：US11590620

申请日：2006-10-31

申请人： Wook-Hyun Kwon ,  Chan-Kwang Park ,  Sang-Pil Sim

发明人： Wook-Hyun Kwon ,  Chan-Kwang Park ,  Sang-Pil Sim

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

公开(公告)号：US07586135B2

公开(公告)日：2009-09-08

申请号：US11606569

申请日：2006-11-30

申请人： Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Soon-Moon Jung ,  Sang-Pil Sim

发明人： Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Soon-Moon Jung ,  Sang-Pil Sim

IPC分类号： H01L29/80

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

摘要翻译： 包括多个半导体层的半导体器件。 多个晶体管位于每个半导体层上。 晶体管包括栅极线，并且在包括晶体管的相应半导体层中的栅极线之间形成源极区和漏极区。 半导体器件还包括多个本地源极线结构。 局部源极线结构中的每一个位于相应的一个半导体层上，并连接形成在相应一个半导体层上的多个源极区。 还提供了形成半导体器件的方法。

公开(公告)号：US07276415B2

公开(公告)日：2007-10-02

申请号：US11590620

申请日：2006-10-31

申请人： Wook-Hyun Kwon ,  Chan-Kwang Park ,  Sang-Pil Sim

发明人： Wook-Hyun Kwon ,  Chan-Kwang Park ,  Sang-Pil Sim

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

摘要翻译： 一种形成非接触非易失性存储器件的方法包括：制备包括单元阵列区域的半导体衬底，在单元阵列区域中的半导体衬底上形成彼此平行的多个掩模图案，使用掩模图案蚀刻半导体衬底 蚀刻掩模以形成多个凹陷区域，在所述凹陷区域的侧壁和底部上形成栅极绝缘层，在所述半导体衬底的上表面上形成浮栅，以填充所述凹陷区域，将所述浮栅层平坦化为 露出掩模图案的上表面并在凹陷区域中形成浮置栅极图案，在掩模图案之下的半导体衬底中形成掩埋的杂质扩散区域，形成栅间电介质层，形成控制栅极层，以及图案化控制栅极层 ，隔间电介质层和浮栅图案，以形成多个平行 与文字线和凹槽区域之间的浮动栅极以及浮动栅极和字线之间的隔间电介质图案，以及露出凹槽区域和字线之间的掩模图案。

公开(公告)号：US20070176214A1

公开(公告)日：2007-08-02

申请号：US11606569

申请日：2006-11-30

申请人： Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Soon-Moon Jung ,  Sang-Pil Sim

发明人： Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Soon-Moon Jung ,  Sang-Pil Sim

IPC分类号： H01L29/768

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

摘要翻译： 包括多个半导体层的半导体器件。 多个晶体管位于每个半导体层上。 晶体管包括栅极线，并且在包括晶体管的相应半导体层中的栅极线之间形成源极区和漏极区。 半导体器件还包括多个本地源极线结构。 局部源极线结构中的每一个位于相应的一个半导体层上，并连接形成在相应一个半导体层上的多个源极区。 还提供了形成半导体器件的方法。

公开(公告)号：US20090200596A1

公开(公告)日：2009-08-13

申请号：US12417127

申请日：2009-04-02

申请人： Sang-Pil Sim ,  Kwang-soo Kim ,  Chan-Kwang Park ,  Heon-Kyu Lee

发明人： Sang-Pil Sim ,  Kwang-soo Kim ,  Chan-Kwang Park ,  Heon-Kyu Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114

摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

摘要翻译： 制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。 该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。 该方法包括蚀刻半导体衬底的至少一部分，其部分地包括凹陷区域并形成深度不同，与凹陷区域相交并彼此连接的第一和第二沟槽。 该方法包括形成具有粗糙底部的器件隔离层，并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。 该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层，并在栅极绝缘层上形成栅极结构，以填充凹陷区域，栅极结构包括浮置栅极，栅极间绝缘图案， 和控制门。

公开(公告)号：US20070122968A1

公开(公告)日：2007-05-31

申请号：US11583796

申请日：2006-10-20

申请人： Sang-Pil Sim ,  Kwang-soo Kim ,  Chan-Kwang Park ,  Heon-Kyu Lee

发明人： Sang-Pil Sim ,  Kwang-soo Kim ,  Chan-Kwang Park ,  Heon-Kyu Lee

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

摘要翻译： 制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。 该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。 该方法包括蚀刻半导体衬底的至少一部分，其部分地包括凹陷区域并形成深度不同，与凹陷区域相交并彼此连接的第一和第二沟槽。 该方法包括形成具有粗糙底部的器件隔离层，并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。 该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层，并在栅极绝缘层上形成栅极结构，以填充凹陷区域，栅极结构包括浮置栅极，栅极间绝缘图案， 和控制门。

公开(公告)号：US07531409B2

公开(公告)日：2009-05-12

申请号：US11583796

申请日：2006-10-20

申请人： Sang-Pil Sim ,  Kwang-soo Kim ,  Chan-Kwang Park ,  Heon-Kyu Lee

发明人： Sang-Pil Sim ,  Kwang-soo Kim ,  Chan-Kwang Park ,  Heon-Kyu Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

摘要翻译： 制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。 该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。 该方法包括蚀刻半导体衬底的至少一部分，其部分地包括凹陷区域并形成深度不同，与凹陷区域相交并彼此连接的第一和第二沟槽。 该方法包括形成具有粗糙底部的器件隔离层，并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。 该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层，并在栅极绝缘层上形成栅极结构，以填充凹陷区域，栅极结构包括浮置栅极，栅极间绝缘图案， 和控制门。

公开(公告)号：US20140353769A1

公开(公告)日：2014-12-04

申请号：US14463394

申请日：2014-08-19

申请人： Shigenobu Maeda ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

发明人： Shigenobu Maeda ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC分类号： H01L29/10 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/0692 ,  B82Y10/00 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

公开(公告)号：US20060030102A1

公开(公告)日：2006-02-09

申请号：US11021232

申请日：2004-12-23

申请人： Chang-Hyun Lee ,  Sang-Pil Sim ,  Seung-Keun Lee

发明人： Chang-Hyun Lee ,  Sang-Pil Sim ,  Seung-Keun Lee

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.

摘要翻译： 闪存集成电路器件包括集成电路基板。 集成电路基板上的单元阵列包括多个单元晶体管。 位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。 第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。 一个或多个第二传输晶体管耦合到第一传输晶体管。 第二传输晶体管具有第二扩散结构。 第二扩散结构可以具有小于第一扩散结构的电阻的电阻。