公开(公告)号：US20130105942A1

公开(公告)日：2013-05-02

申请号：US13287331

申请日：2011-11-02

申请人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

发明人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L28/20 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/94

摘要： Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

摘要翻译： 公开了FinFET半导体器件的各种实施例。 可以形成一对共用的源极，漏极和/或沟道的匹配电容器。 因此，可以制造每个电容器的电容特性使得它们彼此相似。 还描述了采用FinFET技术制造的电阻器。 电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

公开(公告)号：US09293584B2

公开(公告)日：2016-03-22

申请号：US13287331

申请日：2011-11-02

申请人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

发明人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC分类号： H01L29/785 ,  H01L28/20 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/94

摘要： Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

摘要翻译： 公开了FinFET半导体器件的各种实施例。 可以形成一对共用的源极，漏极和/或沟道的匹配电容器。 因此，可以制造每个电容器的电容特性使得它们彼此相似。 还描述了采用FinFET技术制造的电阻器。 电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

公开(公告)号：US09082751B2

公开(公告)日：2015-07-14

申请号：US13232737

申请日：2011-09-14

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/4236 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835 ,  H01L29/785

摘要： According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

摘要翻译： 根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。 半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。 连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。 一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域， 从而导致半FinFET结构具有降低的导通电阻。

公开(公告)号：US08659081B2

公开(公告)日：2014-02-25

申请号：US13613864

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08455977B2

公开(公告)日：2013-06-04

申请号：US13466986

申请日：2012-05-08

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

摘要翻译： 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

公开(公告)号：US20130001687A1

公开(公告)日：2013-01-03

申请号：US13613864

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20120039106A1

公开(公告)日：2012-02-16

申请号：US13283418

申请日：2011-10-27

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/08

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US08866258B2

公开(公告)日：2014-10-21

申请号：US12587482

申请日：2009-10-06

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L27/08 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49822 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2924/15311

摘要： According to an exemplary embodiment, an interposer structure for electrically coupling a semiconductor die to a support substrate in a semiconductor package includes at least one through-wafer via extending through a semiconductor substrate, where the at least one through-wafer via provides an electrical connection between the semiconductor die and the support substrate. The interposer structure further includes a passive component including a trench conductor, where the trench conductor extends through the semiconductor substrate. The passive component further includes a dielectric liner situated between the trench conductor and the semiconductor substrate. The passive component can further include at least one conductive pad for electrically coupling the trench conductor to the semiconductor die. The passive component can be, for example, an inductor or an antenna.

摘要翻译： 根据示例性实施例，用于将半导体管芯电耦合到半导体封装中的支撑衬底的插入器结构包括延伸穿过半导体衬底的至少一个贯通晶片，其中至少一个贯通晶片通孔提供电连接 在半导体管芯和支撑衬底之间。 插入器结构还包括无源部件，其包括沟槽导体，其中沟槽导体延伸穿过半导体衬底。 无源部件还包括位于沟槽导体和半导体衬底之间的电介质衬垫。 无源部件还可以包括至少一个用于将沟槽导体电耦合到半导体管芯的导电焊盘。 无源部件可以是例如电感器或天线。

公开(公告)号：US08836032B2

公开(公告)日：2014-09-16

申请号：US13277547

申请日：2011-10-20

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/12 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L2029/7857

摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.

摘要翻译： 根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。 鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。 翅片通道相对于第一和第二端子较低掺杂。 通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。 门可以在鳍通道的至少两侧。 在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。

公开(公告)号：US20130082330A1

公开(公告)日：2013-04-04

申请号：US13250563

申请日：2011-09-30

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/092 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

摘要翻译： 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。