公开(公告)号：US20110062563A1

公开(公告)日：2011-03-17

申请号：US12560727

申请日：2009-09-16

申请人： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

发明人： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

IPC分类号： H01L23/495 ,  H01L21/44 ,  H01L23/52

CPC分类号： H05K3/28 ,  G11C16/0483 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/83191 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/24 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3452 ,  H05K2201/0166 ,  H05K2201/0769 ,  H05K2201/10159 ,  H05K2201/10575 ,  H05K2203/049 ,  H05K2203/1316 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided.

摘要翻译： 移动离子扩散导致存储芯片中的非易失性存储元件的阈值电压的偏移，例如在存储器芯片的组装过程中。 为了减少或避免这种偏移，可以将涂层施加到印刷电路板基板或表面安装存储芯片的引导框架。 可以使用厚度约为10μm的丙烯酸树脂涂层。 使用粘合膜将记忆芯片附着到涂层上。 也可以使用堆叠的芯片。 另一种方法在焊接掩模层内提供印刷电路板的铜迹线上的金属阻挡迹线。 金属阻挡迹线以与铜迹线相同的图案制造，但是更宽，使得它们至少部分地包围和包围铜迹线。 提供相应的装置和制造工艺。

公开(公告)号：US07944029B2

公开(公告)日：2011-05-17

申请号：US12560727

申请日：2009-09-16

申请人： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

发明人： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

IPC分类号： H01L23/48

CPC分类号： H05K3/28 ,  G11C16/0483 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/83191 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/24 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3452 ,  H05K2201/0166 ,  H05K2201/0769 ,  H05K2201/10159 ,  H05K2201/10575 ,  H05K2203/049 ,  H05K2203/1316 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided.

摘要翻译： 移动离子扩散导致存储芯片中的非易失性存储元件的阈值电压的偏移，例如在存储器芯片的组装过程中。 为了减少或避免这种偏移，可以将涂层施加到印刷电路板基板或表面安装存储芯片的引导框架。 可以使用厚度约为10μm的丙烯酸树脂涂层。 使用粘合膜将记忆芯片附着到涂层上。 也可以使用堆叠的芯片。 另一种方法在焊接掩模层内提供印刷电路板的铜迹线上的金属阻挡迹线。 金属阻挡迹线以与铜迹线相同的图案制造，但是更宽，使得它们至少部分地包围和包围铜迹线。 提供相应的装置和制造工艺。

公开(公告)号：US08179717B2

公开(公告)日：2012-05-15

申请号：US12569869

申请日：2009-09-29

申请人： Zac Shepard ,  Xiaoyu Yang ,  Albert Meeks ,  Qing Li ,  Enosh Levi ,  Kim Le ,  Raz Dan ,  Brian Murphy

发明人： Zac Shepard ,  Xiaoyu Yang ,  Albert Meeks ,  Qing Li ,  Enosh Levi ,  Kim Le ,  Raz Dan ,  Brian Murphy

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5621 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2924/01013 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the previously-erased blocks are returned to the erased state. The threshold voltage of storage elements of the preloaded blocks can change during the surface mounting process due to a global charge effect phenomenon. The effect is most prominent for higher state storage elements which are surrounded by erased blocks, in a chip for which the wafer backside was thinned and polished. The erased blocks can be programmed using a single program pulse without performing a verify operation, as a wide threshold voltage distribution is acceptable.

摘要翻译： 通过将擦除的块编程为更高的阈值电压电平来准备用于在焊料回流过程中表面安装到衬底的非易失性存储器芯片封装，以改善例如由电子器件制造商预装载内容的块的数据保留。 在表面安装之后，先前擦除的块返回到擦除状态。 由于全局充电效应现象，预载块的存储元件的阈值电压可能在表面贴装过程中发生变化。 对于被擦除块包围的较高状态存储元件，晶片背面被薄化和抛光的芯片中的效果最为突出。 擦除的块可以使用单个编程脉冲编程，而不执行验证操作，因为宽的阈值电压分布是可接受的。

公开(公告)号：US20110075482A1

公开(公告)日：2011-03-31

申请号：US12569869

申请日：2009-09-29

申请人： Zac Shepard ,  Xiaoyu Yang ,  Albert Meeks ,  Qing Li ,  Enosh Levi ,  Kim Le ,  Raz Dan ,  Brian Murphy

发明人： Zac Shepard ,  Xiaoyu Yang ,  Albert Meeks ,  Qing Li ,  Enosh Levi ,  Kim Le ,  Raz Dan ,  Brian Murphy

IPC分类号： G11C16/04 ,  G11C5/02

CPC分类号： G11C11/5621 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2924/01013 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the previously-erased blocks are returned to the erased state. The threshold voltage of storage elements of the preloaded blocks can change during the surface mounting process due to a global charge effect phenomenon. The effect is most prominent for higher state storage elements which are surrounded by erased blocks, in a chip for which the wafer backside was thinned and polished. The erased blocks can be programmed using a single program pulse without performing a verify operation, as a wide threshold voltage distribution is acceptable.

摘要翻译： 通过将擦除的块编程为更高的阈值电压电平来准备用于在焊料回流过程中表面安装到衬底的非易失性存储器芯片封装，以改善例如由电子器件制造商预装载内容的块的数据保留。 在表面安装之后，先前擦除的块返回到擦除状态。 由于全局充电效应现象，预载块的存储元件的阈值电压可能在表面贴装过程中发生变化。 对于被擦除块包围的较高状态存储元件，晶片背面被薄化和抛光的芯片中的效果最为突出。 擦除的块可以使用单个编程脉冲编程，而不执行验证操作，因为宽的阈值电压分布是可接受的。

公开(公告)号：US20090003083A1

公开(公告)日：2009-01-01

申请号：US11819562

申请日：2007-06-28

申请人： Albert Meeks ,  Xiaoyu Yang ,  Kim Le

发明人： Albert Meeks ,  Xiaoyu Yang ,  Kim Le

IPC分类号： G11C11/34

CPC分类号： H01L27/10 ,  G11C11/5671 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/685

摘要： A two terminal nonvolatile memory cell includes a first electrode, a second electrode, a charge storage medium, and a resistive element. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes. A presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.

摘要翻译： 双端非易失性存储单元包括第一电极，第二电极，电荷存储介质和电阻元件。 电荷存储介质和电阻元件在第一和第二电极之间并联连接。 存储在电荷存储介质中的电荷的存在或不存在影响电阻元件的电阻率。

公开(公告)号：US07701746B2

公开(公告)日：2010-04-20

申请号：US11819561

申请日：2007-06-28

申请人： Albert Meeks ,  Xiaoyu Yang ,  Kim Le

发明人： Albert Meeks ,  Xiaoyu Yang ,  Kim Le

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5671 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/1052 ,  H01L29/8616 ,  H01L29/88

摘要： A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes, and a presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.

摘要翻译： 制造双端子非易失性存储单元的方法包括形成第一电极，形成电荷存储介质，形成电阻元件，以及形成第二电极。 电荷存储介质和电阻元件在第一和第二电极之间并联连接，并且存储在电荷存储介质中的电荷的存在或不存在影响电阻元件的电阻率。

公开(公告)号：US20090003082A1

公开(公告)日：2009-01-01

申请号：US11819561

申请日：2007-06-28

申请人： Albert Meeks ,  Xiaoyu Yang ,  Kim Le

发明人： Albert Meeks ,  Xiaoyu Yang ,  Kim Le

IPC分类号： H01L21/8246 ,  G11C11/34

CPC分类号： H01L27/101 ,  G11C11/5671 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/1052 ,  H01L29/8616 ,  H01L29/88

摘要： A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes, and a presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.

摘要翻译： 制造双端子非易失性存储单元的方法包括形成第一电极，形成电荷存储介质，形成电阻元件，以及形成第二电极。 电荷存储介质和电阻元件在第一和第二电极之间并联连接，并且存储在电荷存储介质中的电荷的存在或不存在影响电阻元件的电阻率。

公开(公告)号：US20070069241A1

公开(公告)日：2007-03-29

申请号：US11173973

申请日：2005-07-01

申请人： Xiaoyu Yang ,  Roy Scheuerlein ,  Feng Li ,  Albert Meeks

发明人： Xiaoyu Yang ,  Roy Scheuerlein ,  Feng Li ,  Albert Meeks

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L45/12 ,  G11C17/00 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L45/04 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example hafnium silicon oxynitride or hafnium silicon oxide are particularly effective. Diode materials with band gaps lower than silicon, such as germanium or a silicon-germanium alloy are particularly effective.

摘要翻译： 通过使用具有比二氧化硅更高的介电常数和更高的加速因子的反熔丝材料，并且通过使用具有比硅更低的带隙的二极管，可以使具有包括二极管和反熔丝的存储单元的存储器阵列更小并且在较低的电压下编程。 这样的存储器阵列可以通过使用高加速因子和较低带隙材料而具有长的工作寿命。 具有介于5和27之间的介电常数的防腐材料，例如铪硅氮氧化物或氧化铪铪是特别有效的。 带隙低于硅的二极管材料，例如锗或硅 - 锗合金是特别有效的。