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公开(公告)号：US11456047B2
公开(公告)日：2022-09-27
申请号：US17190575
申请日：2021-03-03
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Huangpeng Zhang , Shiyang Yang , Yu Wang , Huamin Cao , Ting Li , Xu Hou
IPC: G11C29/42 , G11C7/20 , G11C29/44 , G11C29/00 , H03K19/17728
Abstract: Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.
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公开(公告)号：US12026514B1
公开(公告)日：2024-07-02
申请号：US18148214
申请日：2022-12-29
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Huangpeng Zhang
IPC: G06F9/30
CPC classification number: G06F9/3013 , G06F9/30134
Abstract: Disclosed herein are memory device, method for managing a storage system. In an aspect, a memory device comprises an address register to store addresses and a processor coupled to the address register. The processor is configured to receive a first multi-plane program operation command of a set of multi-plane program operation commands. The processor is further configured to latch a first address of the first multi-plane program operation command into the address register. In addition, the processor is further configured to receive a read operation command that includes a second address and refrain from latching the second address into the address register.
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公开(公告)号：US20250054565A1
公开(公告)日：2025-02-13
申请号：US18495696
申请日：2023-10-26
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Zhefan Li , Xiaodong Mei , Huangpeng Zhang , Yu Wang
IPC: G11C29/00
Abstract: Examples of the present application provide operation methods of memories, memory devices and systems. In an example, an operation method includes: in response to a first defective memory cell row of a plurality of memory cell rows in the memory being repaired before packaging, invalidating, in a post-package repair mode, a first repair strategy for repairing the first defective memory cell row before packaging, and configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy.
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公开(公告)号：US20240145007A1
公开(公告)日：2024-05-02
申请号：US18404690
申请日：2024-01-04
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Huangpeng Zhang , Zhichao Du , Ke Jiang , Cong Luo , Daesik Song
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/0483 , G11C16/08 , H10B43/27
Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.
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Patent Agency Ranking
公开(公告)号：US11990900B2
公开(公告)日：2024-05-21
申请号：US17483473
申请日：2021-09-23
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Huangpeng Zhang , Shiyang Yang
CPC classification number: H03K19/0005 , G11C16/0483 , G11C16/06 , G11C29/50008
Abstract: In certain aspects, a circuit for ZQ resistor calibration can include a first input configured to receive a first default configuration. The circuit can also include a second input configured to receive a first calibration value based on a first comparison. The circuit can further include a first output configured to provide a first resistor code for a first resistor category. The circuit can additionally include a second output configured to provide a second resistor code for a second resistor category different from the first resistor category. The circuit can also include a first logic circuit configured to receive a signal from the first input and a signal from the second input, and provide a signal to the first output. The signal to the first output can include the first resistor code. The first resistor code can be different from the second resistor code.
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公开(公告)号：US20240144982A1
公开(公告)日：2024-05-02
申请号：US17993653
申请日：2022-11-23
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Debo Wei , Huangpeng Zhang , Jinze Song , Xiaodong Mei
CPC classification number: G11C7/1057 , G11C7/1078 , H03K19/0005 , G11C2207/105
Abstract: A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value
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公开(公告)号：US11908522B2
公开(公告)日：2024-02-20
申请号：US17488701
申请日：2021-09-29
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Huangpeng Zhang , Zhichao Du , Ke Jiang , Cong Luo , Daesik Song
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C11/5671 , H10B43/27
Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.
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公开(公告)号：US20230069200A1
公开(公告)日：2023-03-02
申请号：US17488701
申请日：2021-09-29
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Huangpeng Zhang , Zhichao Du , Ke Jiang , Cong Luo , Daesik Song
Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.
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公开(公告)号：US20220321122A1
公开(公告)日：2022-10-06
申请号：US17483473
申请日：2021-09-23
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Huangpeng Zhang , Shiyang Yang
Abstract: In certain aspects, a circuit for ZQ resistor calibration can include a first input configured to receive a first default configuration. The circuit can also include a second input configured to receive a first calibration value based on a first comparison. The circuit can further include a first output configured to provide a first resistor code for a first resistor category. The circuit can additionally include a second output configured to provide a second resistor code for a second resistor category different from the first resistor category. The circuit can also include a first logic circuit configured to receive a signal from the first input and a signal from the second input, and provide a signal to the first output. The signal to the first output can include the first resistor code. The first resistor code can be different from the second resistor code.
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