公开(公告)号：US20170133398A1

公开(公告)日：2017-05-11

申请号：US15218421

申请日：2016-07-25

申请人： YOUNG HWAN SON ,  YOUNG WOO PARK ,  JAE DUK LEE

发明人： YOUNG HWAN SON ,  YOUNG WOO PARK ,  JAE DUK LEE

IPC分类号： H01L27/115 ,  G11C16/14 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L23/528 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

公开(公告)号：US20170294443A1

公开(公告)日：2017-10-12

申请号：US15626395

申请日：2017-06-19

申请人： JONG WON KIM ,  SEUNG HYUN LIM ,  CHANG SEOK KANG ,  YOUNG WOO PARK ,  DAE HOON BAE ,  DONG SEOG EUN ,  WOO SUNG LEE ,  JAE DUK LEE ,  JAE WOO LIM ,  HANMEI CHOI

发明人： JONG WON KIM ,  SEUNG HYUN LIM ,  CHANG SEOK KANG ,  YOUNG WOO PARK ,  DAE HOON BAE ,  DONG SEOG EUN ,  WOO SUNG LEE ,  JAE DUK LEE ,  JAE WOO LIM ,  HANMEI CHOI

IPC分类号： H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11529

CPC分类号： H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.