公开(公告)号：US08638609B2

公开(公告)日：2014-01-28

申请号：US12783351

申请日：2010-05-19

申请人： Ya-Fen Lin ,  Colin Bill ,  Takao Akaogi ,  Youseok Suh

发明人： Ya-Fen Lin ,  Colin Bill ,  Takao Akaogi ,  Youseok Suh

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.

摘要翻译： 存储器系统被编程为在自增强期间具有最少的程序干扰和减少的结和通道泄漏。 在将程序信号施加到所选择的字线之前，预充电偏置信号被施加到与所选字线相邻的字线，并且将通过信号施加到剩余的字线。 预充电偏压信号将预充电施加到存储器单元。 选择预充电偏压信号以改善与所选字线相邻的字线上的存储器单元的隔离，提高自升压效率并减少电流泄漏以防止或减少程序干扰和/或编程错误，特别是在禁止的存储器 所选字线上的单元格。

公开(公告)号：US06960783B2

公开(公告)日：2005-11-01

申请号：US10436786

申请日：2003-05-13

申请人： Zhida Lan ,  Colin Bill ,  Michael A. VanBuskirk

发明人： Zhida Lan ,  Colin Bill ,  Michael A. VanBuskirk

IPC分类号： G11C11/56 ,  G11C13/02 ,  H01L35/24

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0009 ,  G11C13/0016 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/71

摘要： An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.

摘要翻译： 公开了一种由在两个电极之间具有选择性导电介质的两个电极制成的有机存储单元。 选择性导电介质包含有机层和无源层。 选择性导电介质通过施加偏置电压来编程，该偏置电压为存储器单元编程期望的阻抗状态。 期望的阻抗状态表示信息的一个或多个位，并且存储单元不需要恒定的功率或刷新周期来保持所需的阻抗状态。 此外，通过施加电流并读取介质的阻抗来读取选择性导电介质，以便确定存储单元的阻抗状态。 还公开了制造有机存储器件/单元的方法，使用有机存储器件/单元的方法，以及诸如包含有机存储器件/单元的计算机的器件。

公开(公告)号：US06275415B1

公开(公告)日：2001-08-14

申请号：US09416563

申请日：1999-10-12

申请人： Sameer S. Haddad ,  Ravi S. Sunkavalli ,  Wing Han Leung ,  John Chen ,  Ravi Prakash Gutala ,  Colin Bill ,  Vei-Han Chan

发明人： Sameer S. Haddad ,  Ravi S. Sunkavalli ,  Wing Han Leung ,  John Chen ,  Ravi Prakash Gutala ,  Colin Bill ,  Vei-Han Chan

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that VDS does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.

摘要翻译： 一种具有多个存储单元的存储器件，每个存储体具有多个存储器单元，以及一种编程器件中的多个存储器单元的方法，其中偏置电压施加到多个存储器单元的公共源极端子，并且将时变电压施加到 要编程的存储单元。 在一个实施例中，施加到要编程的存储器单元的栅极的电压是斜坡电压。 在第二实施例中，施加到待编程的存储器单元的栅极的电压是增加的阶梯电压。 在另一个实施例中，选择施加到公共源极端子的偏置电压和施加到要编程的存储器单元的控制栅极的电压，使得流过被编程的单元的电流减小，并且来自存储器单元的泄漏电流 不被编程的基本上被消除。 在另一个实施例中，将偏置电压施加到公共源极端子，并将偏置电压施加到公共井电压。 施加到控制栅极和源极的电压的组合减少了位线上的负载，以确保VDS不会降低到在编程期间维持热载流子效应所需的水平。 偏置电压也可以施加到存储单元的阱，同时公共源极保持在地。 编程栅极电压的反馈控制可用于控制编程所需的功率。

公开(公告)号：US07259039B2

公开(公告)日：2007-08-21

申请号：US10818261

申请日：2004-04-02

申请人： Zhida Lan ,  Michael A. Van Buskirk ,  Colin Bill

发明人： Zhida Lan ,  Michael A. Van Buskirk ,  Colin Bill

IPC分类号： H01L51/40

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/24 ,  H01L27/28 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0077 ,  H01L51/0085 ,  H01L51/0595

摘要： A memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an active low conductive layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

摘要翻译： 公开了由在两个电极之间具有可控导电介质的两个电极制成的存储单元。 可控导电介质包含有源低导电层和无源层。 当施加外部刺激（例如施加的电场）时，可控导电介质改变其阻抗。 还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

公开(公告)号：US07028240B1

公开(公告)日：2006-04-11

申请号：US10200526

申请日：2002-07-22

申请人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Colin Bill

发明人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Colin Bill

IPC分类号： G01R3/28

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/16

摘要： In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.

摘要翻译： 在用于诊断用于测试在半导体衬底上制造的闪存单元的后端状态机的方法和系统中，在半导体衬底上制造信号选择器和诊断匹配逻辑。 诊断匹配逻辑根据后端状态机的控制变量将生成的匹配输出设置为通过或失败状态。 如果调用诊断模式，则信号选择器选择要在BIST（内置自检）模式的验证步骤中使用的生成的匹配输出。 后端状态机利用生成的匹配输出执行多个BIST模式，用于测试后端状态机的功能。

公开(公告)号：US20060067105A1

公开(公告)日：2006-03-30

申请号：US10983919

申请日：2004-11-08

申请人： Tzu-Ning Fang ,  Michael Van Buskirk ,  Colin Bill

发明人： Tzu-Ning Fang ,  Michael Van Buskirk ,  Colin Bill

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/5664 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.

摘要翻译： 采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。 本发明用于单个存储器单元装置和存储单元阵列。 使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。 使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

公开(公告)号：US06943370B2

公开(公告)日：2005-09-13

申请号：US10882538

申请日：2004-06-30

申请人： Michael A. VanBuskirk ,  Colin Bill ,  Tzu-Ning Fang ,  Zhida Lan

发明人： Michael A. VanBuskirk ,  Colin Bill ,  Tzu-Ning Fang ,  Zhida Lan

IPC分类号： G11C11/56 ,  G11C13/02 ,  G11C16/02 ,  H01L51/00

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0016 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

摘要翻译： 本发明通过帮助单个器件改变半导体阵列中的状态的方式来帮助半导体器件。 可以将状态变化电压施加到半导体器件阵列中的单个器件，而不需要晶体管型电压控制。 本发明的二极体效应通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进该活动。 以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。 本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

公开(公告)号：US06847047B2

公开(公告)日：2005-01-25

申请号：US10287363

申请日：2002-11-04

申请人： Michael A. VanBuskirk ,  Colin Bill ,  Tzu-Ning Fang ,  Zhida Lan

发明人： Michael A. VanBuskirk ,  Colin Bill ,  Tzu-Ning Fang ,  Zhida Lan

IPC分类号： G11C11/56 ,  G11C13/02 ,  G11C16/02 ,  H01L51/00

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0016 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

摘要翻译： 本发明通过帮助单个器件改变半导体阵列中的状态的方式来帮助半导体器件。 可以将状态变化电压施加到半导体器件阵列中的单个器件，而不需要晶体管型电压控制。 本发明的二极体效应通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进该活动。 以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。 本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

公开(公告)号：US6122198A

公开(公告)日：2000-09-19

申请号：US413182

申请日：1999-10-05

申请人： Sameer Shafiq Haddad ,  Ravi Prakash Gutala ,  Colin Bill

发明人： Sameer Shafiq Haddad ,  Ravi Prakash Gutala ,  Colin Bill

IPC分类号： G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

摘要： A method of erase verifying and overerase verifying an array of flash memory cells by erase verifying each memory cell bit-by-bit in a memory array, overerase verifying each memory cell bit-by-bit in the memory array after each memory cell verifies as erased and again erase verifying each memory cell bit-by-bit in the memory array after each cell overerase verifies. The threshold voltage of each memory cell is compared to the threshold voltage of a reference memory cell and an overerase correction pulse is applied to the column in which the overerased memory cell is located.

摘要翻译： 通过擦除存储器阵列中每个存储单元逐位擦除来擦除验证和过度验证闪速存储器单元的方法，每个存储器单元验证为在每个存储器单元中逐位验证每个存储器单元逐位 擦除并再次擦除在每个单元过渡验证后对存储器阵列中的每个存储器单元进行逐位校验。 将每个存储器单元的阈值电压与参考存储单元的阈值电压进行比较，并将高过度校正脉冲施加到高过度存储单元所在的列。

公开(公告)号：US20080062739A1

公开(公告)日：2008-03-13

申请号：US11470958

申请日：2006-09-07

申请人： Colin Bill ,  Mark McClain ,  Michael VanBuskirk

发明人： Colin Bill ,  Mark McClain ,  Michael VanBuskirk

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.

摘要翻译： 提供了一种存储器擦除管理系统，包括提供电阻变化存储单元，将第一行耦合到电阻变化存储单元，将行缓冲器耦合到第一行，提供耦合到行缓冲器的电荷存储装置，以及执行 通过从电荷存储装置通过电阻变化存储单元放电电流来对电阻变化存储单元进行单次脉冲擦除。