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    Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device
    4.
    发明授权
    Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device 有权
    提高制造闪存器件的栅极耦合比（GCR）的方法和结构

    公开(公告)号：US06897116B2

    公开(公告)日：2005-05-24

    申请号：US10660606

    申请日：2003-09-12

    申请人： Wen-Fang Lee ,  Wei-Lun Hsu ,  Chung-Ping Chao ,  Yu-Hsien Lin

    发明人： Wen-Fang Lee ,  Wei-Lun Hsu ,  Chung-Ping Chao ,  Yu-Hsien Lin

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

    摘要： Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.

    摘要翻译： 提供了用于提高用于制造闪速存储器件的栅极耦合比（GCR）的方法和结构。 该方法和结构包括以下步骤。 在所提供的半导体衬底上顺序地形成栅氧化层，第一半导体层和绝缘层。 蚀刻工艺用于蚀刻绝缘层。 然后沉积半导体衬垫并将其用作自对准蚀刻掩模。 在自对准蚀刻之后，去除绝缘层并沉积绝缘堆叠结构。 最后，沉积和蚀刻第二半导体层以形成控制栅区。

    Microelectrode array and method for modifying carbon nanotube electrode interface of the same array
    6.
    发明授权
    Microelectrode array and method for modifying carbon nanotube electrode interface of the same array 有权
    微电极阵列和相同阵列碳纳米管电极界面的修饰方法

    公开(公告)号：US08593052B1

    公开(公告)日：2013-11-26

    申请号：US12638429

    申请日：2009-12-15

    申请人： Shiang-Jie Yen ,  Huan-Chieh Su ,  Tri-Rung Yew ,  Yen-Chung Chang ,  Wei-Lun Hsu ,  Shih-Rung Yeh

    发明人： Shiang-Jie Yen ,  Huan-Chieh Su ,  Tri-Rung Yew ,  Yen-Chung Chang ,  Wei-Lun Hsu ,  Shih-Rung Yeh

    IPC分类号： H01J1/63 ,  H01J63/04 ,  H01J17/49

    CPC分类号： C01B31/0273 ,  A61N1/0502 ,  A61N1/0551 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/174

    摘要： The present invention discloses a method for modifying a carbon nanotube electrode interface, which modifies carbon nanotubes used as a neuron-electrode interface by performing three stages of modifications and comprises the steps of: carboxylating carbon nanotubes to provide carboxyl functional groups and improve the hydrophilicity of the carbon nanotubes; acyl-chlorinating the carboxylated carbon nanotubes to replace the hydroxyl functional groups of the carboxyl functional groups with chlorine atoms; and aminating the acyl-chlorinated carbon nanotubes to replace the chlorine atoms with a derivative having amine functional groups at the terminal thereof. The modified carbon nanotubes used as the neuron-electrode interface has lower impedance and higher adherence to nerve cells. Thus is improved the quality of neural signal measurement. The present invention also discloses a microelectrode array, wherein the neuron-electrode interface uses carbon nanotubes modified according to the method of the present invention.

    摘要翻译： 本发明公开了一种修饰碳纳米管电极界面的方法，其通过进行三个阶段的修饰来改变用作神经元 - 电极界面的碳纳米管，并且包括以下步骤：使碳纳米管羧化以提供羧基官能团并提高其亲水性 碳纳米管; 酰化氯化羧化碳纳米管以用氯原子代替羧基官能团的羟基官能团; 并将酰基氯化碳纳米管胺化以在其末端具有胺官能团的衍生物代替氯原子。 用作神经元 - 电极界面的改性碳纳米管具有较低的阻抗和较高的对神经细胞的依从性。 因此提高了神经信号测量的质量。 本发明还公开了一种微电极阵列，其中神经电极界面使用根据本发明的方法改性的碳纳米管。

    THIN FILM TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    THIN FILM TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管器件及其制造方法

    公开(公告)号：US20120286279A1

    公开(公告)日：2012-11-15

    申请号：US13313023

    申请日：2011-12-07

    申请人： Wei-Lun Hsu ,  Chia-Chun Kao ,  Shou-Peng Weng

    发明人： Wei-Lun Hsu ,  Chia-Chun Kao ,  Shou-Peng Weng

    IPC分类号： H01L21/336 ,  H01L29/786

    CPC分类号： H01L21/268 ,  H01L27/1251

    摘要： A thin film transistor device includes a first conductivity type thin film transistor and a second conductivity type thin film transistor. The first conductivity type thin film transistor includes a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode and a first semiconductor pattern. The second conductivity type thin film transistor includes a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode and a second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer. The first patterned doped layer is disposed under the first semiconductor pattern, and the second patterned doped layer is disposed on the second semiconductor pattern.

    摘要翻译： 薄膜晶体管器件包括第一导电型薄膜晶体管和第二导电型薄膜晶体管。 第一导电型薄膜晶体管包括第一图案化掺杂层，第一栅电极，第一源电极，第一漏电极和第一半导体图案。 第二导电型薄膜晶体管包括第二图案化掺杂层，第二栅电极，第二源电极，第二漏电极和第二半导体图案。 第一半导体图案和第二半导体图案形成图案化的半导体层。 第一图案化掺杂层设置在第一半导体图案下方，并且第二图案化掺杂层设置在第二半导体图案上。

    METHOD FOR OPERATING SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR OPERATING SEMICONDUCTOR DEVICE 有权
    操作半导体器件的方法

    公开(公告)号：US20120038414A1

    公开(公告)日：2012-02-16

    申请号：US13282482

    申请日：2011-10-27

    申请人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    发明人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    IPC分类号： G05F3/02

    CPC分类号： H01L27/085 ,  H01L29/7817 ,  H03F3/195

    摘要： A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

    摘要翻译： 一种用于操作包括具有第一源极，公共漏极和第一栅极的横向双扩散金属氧化物半导体（LDMOS）的半导体器件的方法，具有第二源极的结型场效应晶体管（JFET），所述公共漏极和第二源极 栅极，其中第二源极电连接到第一栅极，并且提供与第一源电连接的内部电路。 第一源为内部电路提供内部电流，以通过横向双扩散金属氧化物半导体产生内部电压，并且当内部电压升高到与第一栅极高相同时，横向双扩散金属氧化物半导体截止 电压。

    Semiconductor device and method for operating the same
    9.
    发明授权
    Semiconductor device and method for operating the same 有权
    半导体装置及其操作方法

    公开(公告)号：US08072011B2

    公开(公告)日：2011-12-06

    申请号：US12573884

    申请日：2009-10-06

    申请人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    发明人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    IPC分类号： H01L29/80 ,  H01L31/112

    CPC分类号： H01L27/085 ,  H01L29/7817 ,  H03F3/195

    摘要： A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

    摘要翻译： 半导体器件包括横向双扩散金属氧化物半导体（LDMOS），结型场效应晶体管（JFET）和内部电路。 横向双扩散金属氧化物半导体包括第一源极，公共漏极和第一栅极。 结型场效应晶体管包括第二源极，公共漏极和第二栅极。 第二源电连接到第一栅极。 内部电路电连接到第一源。