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    Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device
    2.
    发明授权
    Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device 有权
    提高制造闪存器件的栅极耦合比（GCR）的方法和结构

    公开(公告)号：US06897116B2

    公开(公告)日：2005-05-24

    申请号：US10660606

    申请日：2003-09-12

    申请人： Wen-Fang Lee ,  Wei-Lun Hsu ,  Chung-Ping Chao ,  Yu-Hsien Lin

    发明人： Wen-Fang Lee ,  Wei-Lun Hsu ,  Chung-Ping Chao ,  Yu-Hsien Lin

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

    摘要： Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.

    摘要翻译： 提供了用于提高用于制造闪速存储器件的栅极耦合比（GCR）的方法和结构。 该方法和结构包括以下步骤。 在所提供的半导体衬底上顺序地形成栅氧化层，第一半导体层和绝缘层。 蚀刻工艺用于蚀刻绝缘层。 然后沉积半导体衬垫并将其用作自对准蚀刻掩模。 在自对准蚀刻之后，去除绝缘层并沉积绝缘堆叠结构。 最后，沉积和蚀刻第二半导体层以形成控制栅区。

    High-voltage device structure
    7.
    发明授权
    High-voltage device structure 有权
    高压器件结构

    公开(公告)号：US07061029B1

    公开(公告)日：2006-06-13

    申请号：US10906570

    申请日：2005-02-24

    申请人： Wen-Fang Lee ,  Wei-Lun Hsu ,  Yu-Hsien Lin

    发明人： Wen-Fang Lee ,  Wei-Lun Hsu ,  Yu-Hsien Lin

    IPC分类号： H01L29/745

    CPC分类号： H01L29/4238 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7833

    摘要： A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well and the second well respectively, and a gate of a second length on the substrate surface. Since the gate of the second length is longer than the source diffusion region and the drain diffusion region of the first length, the two sides of the gate have two spare regions. Two windows are located in the spare regions.

    摘要翻译： 设置在第一导电类型的衬底中的高电压器件结构包括第一阱和第二阱，第一阱和第二阱中的每一个具有位于第一阱中的第一长度的第二导电类型，源极扩散区和漏极扩散区， 第二阱以及衬底表面上的第二长度的栅极。 由于第二长度的栅极长于第一长度的源极扩散区域和漏极扩散区域，栅极的两侧具有两个备用区域。 两个窗口位于备用区域。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120313175A1

    公开(公告)日：2012-12-13

    申请号：US13156352

    申请日：2011-06-09

    申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

    发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

    摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

    摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。

    High voltage semiconductor device
    9.
    发明授权
    High voltage semiconductor device 有权
    高压半导体器件

    公开(公告)号：US08890144B2

    公开(公告)日：2014-11-18

    申请号：US13414723

    申请日：2012-03-08

    申请人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

    发明人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

    IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

    CPC分类号： H01L27/0629 ,  H01L29/0634

    摘要： A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

    摘要翻译： 高电压半导体器件包括衬底，位于衬底上的绝缘层和位于绝缘层上的硅层。 硅层还包括至少第一掺杂条，分别在硅层的两个相对端形成并电连接到第一掺杂条的两个端子掺杂区和多个第二掺杂条。 第一掺杂带和端子掺杂区包括第一导电类型，第二掺杂条包括第二导电类型，第一导电类型和第二导电类型是互补的。 交替布置第一掺杂条和第二掺杂条。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08698247B2

    公开(公告)日：2014-04-15

    申请号：US13156352

    申请日：2011-06-09

    申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

    发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

    摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

    摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。