-
1.发明申请Device using ambipolar transport in SB-MOSFET and method for operating the same 失效在SB-MOSFET中使用双极传输的器件及其操作方法公开(公告)号：US20060131621A1
公开(公告)日：2006-06-22
申请号：US11187654
申请日：2005-07-22
IPC分类号： H01L31/112
CPC分类号： H01L29/7839 , G11C11/56
摘要： A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (−) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.
摘要翻译： 提供了使用SB-MOSFET的双极运输的装置及其操作方法。 SB-MOSFET包括：硅沟道区; 源极和漏极在沟道区域的两侧接触并由包括金属层的材料形成; 以及形成在沟道区上的栅极，介于其间的栅介质层。 正极（+），0或负（ - ）栅极电压选择性地施加到栅极，当施加负阈值电压和正阈值电压之间的栅极电压时，通道变为截止状态，并且通道变为第一个 当门电压低于负阈值电压或高于正阈值电压时，状态和第二导通状态。 因此，可以实现三种电流状态，即空穴电流，电子电流，无电流。 SB-MOSFET可以应用于多位存储器和/或多位逻辑器件。
-
公开(公告)号：US20060118899A1
公开(公告)日：2006-06-08
申请号：US11196180
申请日：2005-08-03
IPC分类号： H01L31/07
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/872
摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
-
3.发明申请公开(公告)号：US20060131664A1
公开(公告)日：2006-06-22
申请号：US11188076
申请日：2005-07-22
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal suicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译： 提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。 硅层具有沟道区。 栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极电介质层。 双层形成为具有介于硅层之间的沟道区的源极/漏极。
-
4.发明申请公开(公告)号：US20070128781A1
公开(公告)日：2007-06-07
申请号：US11502948
申请日：2006-08-11
IPC分类号： H01L21/338
CPC分类号： H01L29/458 , H01L29/517 , H01L29/66643
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same. The method includes the steps of: preparing a substrate; forming an active silicon layer on the substrate; forming a gate insulating layer on a region of the silicon layer; forming a gate electrode on the gate insulating layer; implanting ions into the silicon layer on which the gate insulating layer is not formed; and annealing the ion-implanted silicon layer. Accordingly, it is possible to manufacture the Schottky barrier tunnel transistor having stable characteristics and high performance by implanting the ions into the silicon layer using an ion implantation method and then annealing the silicon layer to form metal-silicide.
摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法。 该方法包括以下步骤：制备衬底; 在衬底上形成有源硅层; 在所述硅层的区域上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 将离子注入未形成栅极绝缘层的硅层中; 并对离子注入的硅层退火。 因此，通过使用离子注入法将离子注入硅层，然后使硅层退火以形成金属硅化物，可以制造具有稳定特性和高性能的肖特基势垒隧道晶体管。
-
5.发明申请SB-MOSFET (Schottky barrier metal-oxide-semiconductor field effect transistor) with low barrier height and fabricating method thereof 审中-公开具有低势垒高度的SB-MOSFET（肖特基势垒金属氧化物半导体场效应晶体管）及其制造方法公开(公告)号：US20070187758A1
公开(公告)日：2007-08-16
申请号：US11635179
申请日：2006-12-07
IPC分类号： H01L27/12
CPC分类号： H01L29/458 , H01L29/045 , H01L29/66772 , H01L29/7839 , H01L29/78696
摘要： Provided is a high-performance n-type Schottky barrier tunneling transistor with low Schottky barrier for electrons due to a Schottky junction formed on a Si (111) surface created through anisotropic etching. The Schottky barrier tunneling transistor includes: a silicon on insulator (SOI) substrate; a source and a drain formed on the SOI substrate; a channel formed between the source and the drain; a gate insulating layer and a gate electrode sequentially formed on the channel; and a sidewall insulating layer formed on both sidewalls of the gate insulating layer and the gate electrode, wherein an interface between the source/drain and the channel is on a Si (111) in the channel, and the source and drain consists of metal silicide through silicidation with a predetermined metal and forms a Schottky junction with the silicon channel.
摘要翻译： 提供了由于通过各向异性蚀刻形成的Si（111）表面上形成的肖特基结，具有用于电子的肖特基势垒低的高性能n型肖特基势垒隧道晶体管。 肖特基势垒隧道晶体管包括：绝缘体上硅（SOI）衬底; 在SOI衬底上形成的源极和漏极; 在源极和漏极之间形成的沟道; 顺序地形成在沟道上的栅极绝缘层和栅电极; 以及形成在栅极绝缘层和栅极电极的两个侧壁上的侧壁绝缘层，其中源极/漏极和沟道之间的界面在通道中的Si（111）上，并且源极和漏极由金属硅化物 通过与预定金属的硅化，并与硅通道形成肖特基结。
-
6.发明申请公开(公告)号：US20070034951A1
公开(公告)日：2007-02-15
申请号：US11485837
申请日：2006-07-13
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。
-
公开(公告)号：US20060095209A1
公开(公告)日：2006-05-04
申请号：US11259488
申请日：2005-10-26
IPC分类号： G06F19/00
CPC分类号： G01D4/004 , Y02B90/242 , Y04S20/322
摘要： An electronic power-measurement device with intelligent agent includes a power measurement unit, an intelligent agent and a communication unit. The device can commonly assess data necessary for works, as an intelligent agent is mounted on the electronic power-measurement device, although the manufacturers of the devices and hardware structure based on types of the devices are different from each other. Also, the device can select only data suitable to a high level service and can selectively assess thereto, in order to minimize extraction of unnecessary data when assessing data necessary for works, as the entire data structure is previously designed in tree form, such that each step of the tree can be used as address assess to corresponding data.
摘要翻译： 具有智能代理的电子功率测量装置包括功率测量单元，智能代理和通信单元。 尽管基于设备类型的设备和硬件结构的制造商彼此不同，但是该设备可以通常评估工作所需的数据，因为智能代理安装在电子功率测量设备上。 此外，设备可以仅选择适合于高级服务的数据，并且可以选择性地评估它们，以便在评估作品所需的数据时最小化对不需要的数据的提取，因为整个数据结构先前是以树形设计的， 树的步骤可以用作对相应数据的地址评估。
-
公开(公告)号：US20060154454A1
公开(公告)日：2006-07-13
申请号：US10543318
申请日：2004-08-21
CPC分类号： C30B29/403 , C30B25/02 , C30B29/36 , C30B29/406 , H01L21/0242 , H01L21/02447 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/0262 , H01L33/007
摘要： The present invention relates to a method for fabricating a gallium nitride(GaN) based nitride layer including a step of forming a wetting layer having of forming a wetting layer having a composition of In(x1)Ga(y1)N (0
摘要翻译： 本发明涉及一种用于制造氮化镓（GaN）基氮化物层的方法，包括形成具有形成具有In（x1）Ga（y1）N（0
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.021 秒)
