公开(公告)号：US08669172B2

公开(公告)日：2014-03-11

申请号：US13488015

申请日：2012-06-04

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US20060231884A1

公开(公告)日：2006-10-19

申请号：US11402972

申请日：2006-04-13

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在第一浮动栅极和第二浮动栅极之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US07705392B2

公开(公告)日：2010-04-27

申请号：US11402972

申请日：2006-04-13

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US20120238089A1

公开(公告)日：2012-09-20

申请号：US13488015

申请日：2012-06-04

申请人： Yasuaki YONEMOCHI ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki YONEMOCHI ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/283

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US08211777B2

公开(公告)日：2012-07-03

申请号：US12727890

申请日：2010-03-19

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US20100190330A1

公开(公告)日：2010-07-29

申请号：US12727890

申请日：2010-03-19

申请人： Yasuaki YONEMOCHI ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki YONEMOCHI ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/28

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

公开(公告)号：US07972920B2

公开(公告)日：2011-07-05

申请号：US12700344

申请日：2010-02-04

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/8244 ,  G11C11/40

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07402475B2

公开(公告)日：2008-07-22

申请号：US11265292

申请日：2005-11-03

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US07388238B2

公开(公告)日：2008-06-17

申请号：US11452275

申请日：2006-06-14

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/10

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20080049472A1

公开(公告)日：2008-02-28

申请号：US10564025

申请日：2005-04-20

申请人： Akio Nishida ,  Fumi Kitao ,  Hiroshi Takemura

发明人： Akio Nishida ,  Fumi Kitao ,  Hiroshi Takemura

IPC分类号： H02M5/42

CPC分类号： H02M3/3381

摘要： A switching power supply device includes a primary winding of a transformer that is connected in series to a first switching element, and a secondary winding is provided with a rectifier circuit and an output voltage control circuit arranged to detect an output voltage and feed it back to a control circuit. The control circuit is provided with an on-period control circuit arranged to turn off the first switching element in an on-state based on a feedback signal from the output voltage control circuit and an off-period control circuit arranged to control an off-period thereof by delaying turn-on of the first switching element based on the feedback signal.

摘要翻译： 开关电源装置包括与第一开关元件串联连接的变压器的初级绕组，次级绕组设置有整流电路和输出电压控制电路，其布置成检测输出电压并将其馈送回 一个控制电路。 所述控制电路设置有接通时间控制电路，其布置成基于来自所述输出电压控制电路的反馈信号而将所述第一开关元件断开，并且将所述第一开关元件设置为断开时段控制电路， 其基于反馈信号延迟第一开关元件的导通。