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    Semiconductor integrated circuit memory
    2.
    发明授权
    Semiconductor integrated circuit memory 失效
    半导体集成电路存储器

    公开(公告)号：US4954866A

    公开(公告)日：1990-09-04

    申请号：US247250

    申请日：1988-09-21

    申请人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

    发明人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

    IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/0605 ,  H01L27/1116 ,  H01L27/105

    摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.

    摘要翻译： 公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。 例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。 此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。

    Semiconductor integrated circuit device and method of testing the same
    3.
    发明授权
    Semiconductor integrated circuit device and method of testing the same 失效
    半导体集成电路器件及其测试方法

    公开(公告)号：US5068605A

    公开(公告)日：1991-11-26

    申请号：US404355

    申请日：1989-09-07

    申请人： Moritoshi Yasunaga ,  Noboru Masuda ,  Hideo Todokoro ,  Yasunari Umemoto ,  Hirotoshi Tanaka ,  Hiroyuki Itoh

    发明人： Moritoshi Yasunaga ,  Noboru Masuda ,  Hideo Todokoro ,  Yasunari Umemoto ,  Hirotoshi Tanaka ,  Hiroyuki Itoh

    IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/302 ,  G01R31/305 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G01R31/305 ,  G01R31/30 ,  G01R31/318516

    摘要： A semiconductor integrated circuit device includes: input terminals; output terminals; a group of gates which receives an input signal applied to the input terminals and outputs an output signal from the output terminals, the output signal corresponding to the state of the input signal; and an arrangement for forcibly setting the output of each gate constituting the group either at a "1" level or at a "0" level irrespective of the state of the input signal and the state of an input signal to each gate. The arrangement for forcibly setting the output is an arrangement for changing the potential of a semiconductor substrate in which each gate is formed. This arrangement for changing potential includes an impurity doped region formed in the semiconductor substrate, the impurity doped region surrounding at least a transistor constituting each gate so as to apply a potential to the transistor, and a terminal for applying the potential to the impurity doped region. The semiconductor integrated circuit device according to another aspect includes an observation pad formed on a portion of at least one of the output and input areas of each gate, the observation pad being exposed without being covered with an insulator layer and the potential of the observation pad being observed as a difference of shading by using an electron or ion beam tester. A fault of each gate can be detected in accordance with a shading image of the observation pads.

    摘要翻译： 半导体集成电路装置包括：输入端子; 输出端子; 一组门，其接收施加到输入端的输入信号，并输出来自输出端的输出信号，输出信号对应于输入信号的状态; 以及用于强制地将构成组的每个门的输出强制设置为“1”电平或“0”电平的装置，而与输入信号的状态和每个门的输入信号的状态无关。 用于强制设置输出的布置是用于改变其中形成每个栅极的半导体衬底的电位的布置。 这种用于变化电位的布置包括形成在半导体衬底中的杂质掺杂区域，至少构成每个栅极的晶体管的杂质掺杂区域，以便向晶体管施加电位，以及将电位施加到杂质掺杂区域 。 根据另一方面的半导体集成电路器件包括形成在每个栅极的输出和输入区域中的至少一个的一部分上的观察垫，观察垫被暴露而不被绝缘体层覆盖，并且观察垫的电位 通过使用电子或离子束测试仪被观察为阴影的差异。 可以根据观察垫的阴影图像来检测每个门的故障。

    Fluctuation-free input buffer
    4.
    发明授权
    Fluctuation-free input buffer 失效
    无波动输入缓冲器

    公开(公告)号：US4697110A

    公开(公告)日：1987-09-29

    申请号：US555618

    申请日：1983-11-28

    申请人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

    发明人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

    IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0952 ,  H03K17/14 ,  H03K19/094

    CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

    摘要： An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.

    摘要翻译： 用于半导体电路的输入缓冲器设置有源极跟随器电路，该源极跟随器电路由其栅极具有与其连接的输入端的第一FET和与第一FET的导电类型相同的第二FET组成，漏极连接到 直接或通过至少一个电平移位二极管的第一FET的源极，并且其栅电极被提供控制电压。 输入缓冲器还包括直接或通过至少一个电平移位二极管连接到第二FET的漏电极的FET反相器电路。 输入缓冲器的输出信号是从FET反相器电路得出的。 本发明的一个特别优点在于，它允许输入缓冲器响应于处于预定电压范围内的输入信号而将其输出从一个电平切换到另一个电平，而与FET中的逻辑阈值电平波动无关，并且耦合到 输入缓冲区。

    High speed clock distribution system
    5.
    发明授权
    High speed clock distribution system 失效
    高速时钟分配系统

    公开(公告)号：US5087829A

    公开(公告)日：1992-02-11

    申请号：US443503

    申请日：1989-12-01

    申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

    发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

    IPC分类号： H03K5/15

    CPC分类号： H03K5/15

    摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

    摘要翻译： 本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号： 延迟时间被调整的延迟电路组。 时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置 通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系 时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

    Wireless communication restriction device, repeater and base station
    8.
    发明授权
    Wireless communication restriction device, repeater and base station 有权
    无线通信限制设备，中继器和基站

    公开(公告)号：US06987978B2

    公开(公告)日：2006-01-17

    申请号：US10337310

    申请日：2003-01-07

    申请人： Noboru Masuda ,  Takashi Yano ,  Takeshi Kato

    发明人： Noboru Masuda ,  Takashi Yano ,  Takeshi Kato

    IPC分类号： H04M1/00

    CPC分类号： H04B7/1555 ,  H04B7/2606 ,  H04W84/005 ,  H04W84/047

    摘要： The disclosed invention makes mobile terminals physically impossible to use in specific spaces without using radio waves of so high intensity as to affect medical devices and without requiring telephone companies that operate wireless communications systems (WCS) to take special measures. Cooperation of a telephone company on the implementation of making mobile terminals physically impossible to use in specific spaces makes mobile terminals provided by the telephone company easy to use. Pseudo signals of downlink pilot signal in WCS are emitted off the pilot timing in specific spaces. Uplink channel radio waves in cooperative telephone compannies' WCS are relayed and communication path is disconnected if the uplink channel radio waves are for communication of an attribute banned in the space. Communication path can be disconnected without increasing the intensity of radio waves so high. In cooperative telephone compannies' WCS, only the path of communication of an attribute banned in the space is disconnected.

    摘要翻译： 所公开的发明使得移动终端在特定空间中物理上不可能使用，而不使用如此高的强度的无线电波影响医疗设备，并且不需要操作无线通信系统（WCS）的电话公司采取特殊措施。 电话公司在实施移动终端实际上​​不可能在特定空间中使用的合作使得电话公司提供的移动终端易于使用。 WCS中的下行链路导频信号的伪信号在特定空间内从导频定时发出。 如果上行链路信道无线电波用于在空间中禁止的属性的通信，则中继合作电话单元WCS中的上行链路无线电波，并且通信路径被断开。 通信路径可以在不增加无线电波强度的情况下断开连接。 在合作电话公司的WCS中，只有空间中禁止的属性的通信路径才会断开连接。

    Logic circuit
    9.
    发明授权
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US6064234A

    公开(公告)日：2000-05-16

    申请号：US134335

    申请日：1998-08-14

    申请人： Noboru Masuda ,  Yoshio Miki ,  Shun Kawabe

    发明人： Noboru Masuda ,  Yoshio Miki ,  Shun Kawabe

    IPC分类号： H03K19/0948 ,  H03K19/094

    CPC分类号： H03K19/0948

    摘要： A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.

    摘要翻译： 用作具有多个输入和高操作速度的选择器的逻辑电路。 逻辑电路包括：第一FET，具有连接到第一电源的第一电极，连接到输出端子的第二电极和连接到中间控制节点的第三电极;以及并联连接在第二电源 和输出端子。 每个逻辑块包括具有与第一FET相反的导电类型的第二和第三FET，并串联连接在输出端和第二电源之间。 每个逻辑块还包括与第二和第三FET具有相同导电类型的第四FET，并且具有连接到第二FET的第三电极的第三电极，连接到第三FET的第三电极的第一电极和第二FET 电极连接到中间控制节点。 输出端子与第一电源之间的导通电阻降低，并且增加到输出端子的寄生电容也减小，从而允许逻辑电路以高速运行。

    Data transmitter-receiver
    10.
    发明授权
    Data transmitter-receiver 失效
    数据发射机 - 接收机

    公开(公告)号：US5729550A

    公开(公告)日：1998-03-17

    申请号：US618787

    申请日：1996-03-20

    申请人： Kazunori Nakajima ,  Noboru Masuda ,  Tadaaki Isobe ,  Masamori Kashiyama ,  Bunichi Fujita ,  Masakazu Yamamoto

    发明人： Kazunori Nakajima ,  Noboru Masuda ,  Tadaaki Isobe ,  Masamori Kashiyama ,  Bunichi Fujita ,  Masakazu Yamamoto

    IPC分类号： G06F5/06 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20

    CPC分类号： G06F5/06

    摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

    摘要翻译： 在信息处理系统中的多个单元之间发送和接收信号时，可以在由周期（频率）相同但不一定相位的异步时钟操作的电路之间发送和接收信号，从而允许 信息处理系统在较短的时钟周期内运行。 布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。 此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。 延迟电路由决定结果自动控制。