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    Nonvolatile semiconductor memory device and data erasing method thereof
    1.
    发明授权
    Nonvolatile semiconductor memory device and data erasing method thereof 失效
    非易失性半导体存储器件及其数据擦除方法

    公开(公告)号：US5297096A

    公开(公告)日：1994-03-22

    申请号：US711547

    申请日：1991-06-07

    申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： G11C16/14 ,  G11C16/16

    摘要： A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

    摘要翻译： 一种快闪EEPROM，包括分为第一和第二块的存储单元阵列。 为这两个块中的每一个提供擦除用于向存储单元施加擦除脉冲的脉冲施加电路和用于擦除验证存储单元的擦除验证电路。 对应于第一块设置的擦除脉冲施加电路和擦除验证电路与擦除脉冲施加电路和对应于第二块设置的擦除验证电路分开工作。 擦除脉冲施加电路各自由其相应的擦除验证电路控制。 也就是说，每个擦除验证电路仅在检测到相应块中的数据擦除不完整的存储单元时才能使其相应的擦除脉冲施加电路。

    Nonvolatile semiconductor memory device with a row redundancy circuit
    2.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5602778A

    公开(公告)日：1997-02-11

    申请号：US468393

    申请日：1995-06-06

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Nonvolatile semiconductor memory device with a row redundancy circuit
    5.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5548557A

    公开(公告)日：1996-08-20

    申请号：US179731

    申请日：1994-01-11

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Electrically erasable and programmable non-volatile memory device and a method of operating the same
    10.
    发明授权
    Electrically erasable and programmable non-volatile memory device and a method of operating the same 失效
    电可擦除和可编程的非易失性存储器件及其操作方法

    公开(公告)号：US5428568A

    公开(公告)日：1995-06-27

    申请号：US933436

    申请日：1992-08-20

    申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C16/3459

    摘要： In a programming mode of operation of a flash type non-volatile semiconductor memory device, an erase voltage pulse is applied a memory cell to bring the memory cell into an erased state. Then, an after-erase writing operation is executed for a memory cell having a threshold voltage lower than a predetermined threshold voltage under the condition of small change in threshold voltage. Alternatively, an erase voltage pulse is applied only to a memory cell having a threshold voltage greater than a predetermined threshold voltage to carry out erasing. Also, after a memory cell is brought to a depletion state by application of an erase voltage pulse, data writing of "0" and "1" is carried out by injection of electrons into the floating gate. The electron injection rate to the floating gate for writing data "0" is set to be greater than that for writing data "1". The state of storing data "1" corresponds to an erase state. According to this scheme, an excessively erased memory cell does not exist and the distribution range of threshold voltage can be reduced. Furthermore, the reprogramming time period for a memory cell data can be carried out in a short time.

    摘要翻译： 在闪存型非易失性半导体存储器件的编程操作模式中，擦除电压脉冲被施加到存储器单元以使存储单元进入擦除状态。 然后，在阈值电压变化小的条件下，对具有低于预定阈值电压的阈值电压的存储单元执行擦除后写入操作。 或者，擦除电压脉冲仅施加到具有大于预定阈值电压的阈值电压的存储器单元以执行擦除。 此外，在通过施加擦除电压脉冲将存储单元置于耗尽状态之后，通过向浮置栅极注入电子来执行“0”和“1”的数据写入。 写入数据“0”的浮动栅极的电子注入速率被设定为大于写入数据“1”的电子注入速率。 存储数据“1”的状态对应于擦除状态。 根据该方案，不存在过度擦除的存储单元，并且可以减小阈值电压的分布范围。 此外，存储单元数据的重新编程时间段可以在短时间内进行。