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    Nonvolatile semiconductor memory device and data erasing method thereof
    1.
    发明授权
    Nonvolatile semiconductor memory device and data erasing method thereof 失效
    非易失性半导体存储器件及其数据擦除方法

    公开(公告)号：US5297096A

    公开(公告)日：1994-03-22

    申请号：US711547

    申请日：1991-06-07

    申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： G11C16/14 ,  G11C16/16

    摘要： A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

    摘要翻译： 一种快闪EEPROM，包括分为第一和第二块的存储单元阵列。 为这两个块中的每一个提供擦除用于向存储单元施加擦除脉冲的脉冲施加电路和用于擦除验证存储单元的擦除验证电路。 对应于第一块设置的擦除脉冲施加电路和擦除验证电路与擦除脉冲施加电路和对应于第二块设置的擦除验证电路分开工作。 擦除脉冲施加电路各自由其相应的擦除验证电路控制。 也就是说，每个擦除验证电路仅在检测到相应块中的数据擦除不完整的存储单元时才能使其相应的擦除脉冲施加电路。

    Nonvolatile semiconductor memory device with a row redundancy circuit
    2.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5602778A

    公开(公告)日：1997-02-11

    申请号：US468393

    申请日：1995-06-06

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Nonvolatile semiconductor memory device capable of erasing by a word line unit
    4.
    发明授权
    Nonvolatile semiconductor memory device capable of erasing by a word line unit 失效
    能够通过字线单元擦除的非易失性半导体存储器件

    公开(公告)号：US5402382A

    公开(公告)日：1995-03-28

    申请号：US942887

    申请日：1992-09-10

    申请人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    发明人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    IPC分类号： H01L21/8247 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information charge, a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a high voltage generator for generating a negative high voltage. The high voltage generator is connected to each word line and has a capacitor to which a predetermined clock is applied in response to a signal for selecting word lines. The semiconductor memory device further comprises an erasing device, which applies the negative high voltage generated by, the high voltage generator to the word line selected by the selection signal in the erasing operation. The erasing device grounds the source line connected to the source of the corresponding memory cell.

    摘要翻译： 非易失性半导体存储器件具有多个存储单元，它们以具有行和列的矩阵形式布置，并且各自具有用于保持信息电荷的栅极，多个位线，多个字线，多个 源极线和用于产生负高电压的高压发生器。 高电压发生器连接到每个字线，并且响应于用于选择字线的信号，具有施加预定时钟的电容器。 半导体存储器件还包括擦除器件，其在擦除操作中将由高电压发生器产生的负高电压施加到由选择信号选择的字线。 擦除装置将连接到相应存储单元的源的源极线接地。

    Internal voltage generator for a non-volatile semiconductor memory device
    5.
    发明授权
    Internal voltage generator for a non-volatile semiconductor memory device 失效
    用于非易失性半导体存储器件的内部电压发生器

    公开(公告)号：US5371705A

    公开(公告)日：1994-12-06

    申请号：US066300

    申请日：1993-05-24

    申请人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

    发明人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

    IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C17/00 ,  H02M3/07 ,  H03K19/00 ,  G11C7/00

    CPC分类号： G11C5/143 ,  G11C16/12 ,  G11C16/30

    摘要： The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

    摘要翻译： 半导体器件包括用于在第一电源线上选择性地产生第一电平或第二电平的信号的电压发生器，以及使用第一电源线上的电压信号的电压转换器和用于产生电压信号的第二电源线 根据输入信号在第一或第二供电线上的电平;以及电压电平移位器，用于检测第一电源线上的电压电平，使电压电平将第二电源线上的信号移向第一电平 当第一电源线上的电压接近第一电平时。 可以减小第一和第二电源线上的电压差，以改善包括在电压转换器中的晶体管的分解特性，从而获得可靠的半导体器件。

    Nonvolatile semiconductor memory device with a row redundancy circuit
    8.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5548557A

    公开(公告)日：1996-08-20

    申请号：US179731

    申请日：1994-01-11

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。