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    METHOD FOR FORMING DEPOSITED FILM AND PHOTOVOLTAIC ELEMENT
    1.
    发明申请
    METHOD FOR FORMING DEPOSITED FILM AND PHOTOVOLTAIC ELEMENT 有权
    形成沉积膜和光伏元件的方法

    公开(公告)号：US20080096305A1

    公开(公告)日：2008-04-24

    申请号：US11874352

    申请日：2007-10-18

    申请人： Yasuyoshi Takai ,  Hiroshi Shimoda ,  Shotaro Okabe ,  Koichi Matsuda ,  Hidetoshi Tsuzuki

    发明人： Yasuyoshi Takai ,  Hiroshi Shimoda ,  Shotaro Okabe ,  Koichi Matsuda ,  Hidetoshi Tsuzuki

    IPC分类号： H01L21/00

    CPC分类号： H01L21/67253 ,  C23C16/24 ,  C23C16/545 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/076 ,  H01L31/1824 ,  H01L31/202 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

    摘要： A method for forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD includes forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD under conditions such that when a deposited film having a thickness of 300 nm or more is formed on a substrate while the substrate is in a stationary state, an area of the microcrystalline silicon region in which an intensity of Raman scattering attributed to a crystalline substance in the deposited film is equal to or higher than three times an intensity of Raman scattering attributed to an amorphous is 50% or more of the total area based on the area of the microcrystalline silicon region and the area of a region composed of the amorphous.

    摘要翻译： 通过等离子体增强CVD在移动基板上形成含有微晶硅的沉积膜的方法包括通过等离子体增强CVD在移动的衬底上形成含有微晶硅的沉积膜，使得当厚度为300nm的沉积膜 以上，在基板处于静止状态的同时，在基板上形成有由析出膜中的结晶物质引起的拉曼散射强度的微晶硅区域的面积等于或高于 归因于非晶体的拉曼散射基于微晶硅区域的面积和由无定形构成的区域的面积为总面积的50％以上。

    Method for forming deposited film and photovoltaic element
    2.
    发明授权
    Method for forming deposited film and photovoltaic element 有权
    沉积膜和光伏元件的形成方法

    公开(公告)号：US07501305B2

    公开(公告)日：2009-03-10

    申请号：US11874352

    申请日：2007-10-18

    申请人： Yasuyoshi Takai ,  Hiroshi Shimoda ,  Shotaro Okabe ,  Koichi Matsuda ,  Hidetoshi Tsuzuki

    发明人： Yasuyoshi Takai ,  Hiroshi Shimoda ,  Shotaro Okabe ,  Koichi Matsuda ,  Hidetoshi Tsuzuki

    IPC分类号： H01L21/20

    CPC分类号： H01L21/67253 ,  C23C16/24 ,  C23C16/545 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/076 ,  H01L31/1824 ,  H01L31/202 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

    摘要： A method for forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD includes forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD under conditions such that when a deposited film having a thickness of 300 nm or more is formed on a substrate while the substrate is in a stationary state, an area of the microcrystalline silicon region in which an intensity of Raman scattering attributed to a crystalline substance in the deposited film is equal to or higher than three times an intensity of Raman scattering attributed to an amorphous is 50% or more of the total area based on the area of the microcrystalline silicon region and the area of a region composed of the amorphous.

    摘要翻译： 通过等离子体增强CVD在移动基板上形成含有微晶硅的沉积膜的方法包括通过等离子体增强CVD在移动的衬底上形成含有微晶硅的沉积膜，使得当厚度为300nm的沉积膜 以上，在基板处于静止状态的同时，在基板上形成有由析出膜中的结晶物质引起的拉曼散射强度的微晶硅区域的面积等于或高于 归因于非晶体的拉曼散射基于微晶硅区域的面积和由无定形构成的区域的面积为总面积的50％以上。

    Pin junction photovoltaic device having a multi-layered I-type semiconductor layer with a specific non-single crystal I-type layer formed by a microwave plasma CVD process
    5.
    发明授权
    Pin junction photovoltaic device having a multi-layered I-type semiconductor layer with a specific non-single crystal I-type layer formed by a microwave plasma CVD process 失效
    具有具有通过微波等离子体CVD工艺形成的特定非单晶I型层的多层I型半导体层的pin结光电器件

    公开(公告)号：US5676765A

    公开(公告)日：1997-10-14

    申请号：US411225

    申请日：1995-03-27

    申请人： Keishi Saito ,  Koichi Matsuda ,  Hiroshi Shimoda ,  Yusuke Miyamoto

    发明人： Keishi Saito ,  Koichi Matsuda ,  Hiroshi Shimoda ,  Yusuke Miyamoto

    IPC分类号： H01L21/205 ,  H01L31/04 ,  H01L31/052 ,  H01L31/075 ,  H01L31/20

    CPC分类号： H01L31/076 ,  H01L31/056 ,  H01L31/075 ,  H01L31/202 ,  H01L31/206 ,  Y02E10/52 ,  Y02E10/548 ,  Y02P70/521

    摘要： A photovoltaic element comprising a substrate and a multi-layered semiconductor active layer having a pin junction structure disposed on said substrate, said multi-layered semiconductor layer comprising a non-single crystal semiconductor layer of n- or p-type, a non-single crystal i-type semiconductor layer and a non-single crystal semiconductor layer of p- or n-type being stacked in this order from the substrate side, characterized in that said i-type semiconductor layer comprises a three-layered structure comprising a non-single crystal layer (b) formed by means of a microwave plasma CVD process interposed between a pair of non-single crystal layers (a) and (c) each formed by means of a RF plasma CVD process, and said i-type layer (b) is a non-single crystal i-type layer formed by means of the microwave plasma process from a mixture of a silane series gas not containing chlorine atom(s), a chlorine-containing raw material gas in an amount of 10% or less of the total amount of the chlorine-free silane series gas and the chlorine-containing raw material gas, and hydrogen gas.

    摘要翻译： 一种光电元件，包括基板和具有设置在所述基板上的pin结结构的多层半导体有源层，所述多层半导体层包括n型或p型非单晶半导体层，非单晶半导体层 晶体i型半导体层和从衬底侧依次堆叠的p型或n型非单晶半导体层，其特征在于，所述i型半导体层包括三层结构， 通过介于通过RF等离子体CVD工艺形成的一对非单晶层（a）和（c）之间的微波等离子体CVD工艺形成的单晶层（b）和所述i型层（ b）是通过微波等离子体工艺形成的非单晶i型层，其由不含氯原子的硅烷系气体，10％的含氯原料气体的混合物或 少于总量的chl 无水硅烷系列气体和含氯原料气体，以及氢气。

    Process for producing membrane/ electrode assembly for polymer electrolyte fuel cells
    6.
    发明授权
    Process for producing membrane/ electrode assembly for polymer electrolyte fuel cells 有权
    用于生产聚合物电解质燃料电池的膜/电极组件的方法

    公开(公告)号：US08999434B2

    公开(公告)日：2015-04-07

    申请号：US11626534

    申请日：2007-01-24

    申请人： Hiroshi Shimoda ,  Hirokazu Wakabayashi ,  Shinji Kinoshita ,  Toshihiro Tanuma ,  Hideki Nakagawa

    发明人： Hiroshi Shimoda ,  Hirokazu Wakabayashi ,  Shinji Kinoshita ,  Toshihiro Tanuma ,  Hideki Nakagawa

    IPC分类号： B05D5/12 ,  B29C65/00 ,  B32B37/00 ,  H01M8/02 ,  H01M8/10

    CPC分类号： H01M8/1004 ,  H01M8/0245 ,  Y02E60/523

    摘要： A process is provided whereby a membrane/electrode assembly for polymer electrolyte fuel cells whereby a high output voltage is obtainable within a wide range of current densities.A process for producing a membrane/electrode assembly 1 comprising a first electrode 10 having a first catalyst layer 12 and a first gas diffusion layer 14, a second electrode 20 having a second catalyst layer 22 and a second gas diffusion layer 24, and an electrolyte membrane 30, wherein the first gas diffusion layer 14, a first intermediate having the first catalyst layer 12 formed on the surface of the electrolyte membrane 30 by coating followed by annealing, and a second intermediate having the second catalyst layer 22 formed on the surface of the second gas diffusion layer 24 by coating, are bonded, so that the first catalyst layer 12 is located between the first gas diffusion layer 14 and the electrolyte membrane 30, and the second catalyst layer 22 is located between the second gas diffusion layer 24 and the electrolyte membrane 30.

    摘要翻译： 提供了一种方法，由此能够在宽的电流密度范围内获得高输出电压的聚合物电解质燃料电池的膜/电极组件。 包括具有第一催化剂层12和第一气体扩散层14的第一电极10，具有第二催化剂层22和第二气体扩散层24的第二电极20以及电解质 膜30，其中第一气体扩散层14，具有通过涂覆退火而形成在电解质膜30的表面上的第一催化剂层12的第一中间体，以及形成在第二催化剂层22的表面上的第二中间体 通过涂布将第二气体扩散层24接合，使得第一催化剂层12位于第一气体扩散层14和电解质膜30之间，第二催化剂层22位于第二气体扩散层24和 电解质膜30。

    Process for forming catalyst layer, and process for producing membrane/electrode assembly for polymer electrolyte fuel cell
    7.
    发明授权
    Process for forming catalyst layer, and process for producing membrane/electrode assembly for polymer electrolyte fuel cell 有权
    用于形成催化剂层的方法，以及用于生产聚合物电解质燃料电池的膜/电极组件的方法

    公开(公告)号：US08221919B2

    公开(公告)日：2012-07-17

    申请号：US12481261

    申请日：2009-06-09

    申请人： Hiroshi Shimoda ,  Shinji Kinoshita ,  Toshihiro Tanuma ,  Seigo Kotera

    发明人： Hiroshi Shimoda ,  Shinji Kinoshita ,  Toshihiro Tanuma ,  Seigo Kotera

    IPC分类号： H01M4/80 ,  H01M8/10 ,  H01M4/02

    CPC分类号： H01M4/8882 ,  H01M4/8605 ,  H01M4/8807 ,  H01M4/8814 ,  H01M4/8828 ,  H01M8/1007 ,  Y02P70/56

    摘要： In the production of a membrane/electrode assembly 10, a first catalyst layer 22 (a second catalyst layer 34) is formed by a process comprising steps (a) and (b). (a) A step of applying a coating fluid comprising a catalyst and an ion-exchange resin, on a substrate to form a coating fluid layer. (b) A step of disposing a reinforcing layer 24 (34) on the coating fluid layer formed in the step (a) and then, drying the coating fluid layer to form a first catalyst layer 22 (a second catalyst layer 34) The process provides a catalyst layer whereby defects such as cracks are scarcely formed in the catalyst layer, and the bond strength is high at the interface between the catalyst layer and a reinforcing layer and at the interface between the catalyst layer and a polymer electrolyte membrane.

    摘要翻译： 在制造膜/电极组件10时，通过包括步骤（a）和（b）的方法形成第一催化剂层22（第二催化剂层34）。 （a）将包含催化剂和离子交换树脂的涂布液涂布在基材上以形成涂布液层的工序。 （b）在步骤（a）中形成的涂布液层上设置增强层24（34）的步骤，然后干燥涂布液层以形成第一催化剂层22（第二催化剂层34） 提供了催化剂层，其中在催化剂层中几乎不形成诸如裂纹的缺陷，并且在催化剂层和增强层之间以及催化剂层和聚合物电解质膜之间的界面处的结合强度高。

    Non-volatile semiconductor memory device
    8.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US06968435B2

    公开(公告)日：2005-11-22

    申请号：US10418046

    申请日：2003-04-18

    申请人： Hiroshi Shimoda

    发明人： Hiroshi Shimoda

    IPC分类号： G11C16/02 ,  G06F12/00 ,  G06F12/02 ,  G11C16/10

    CPC分类号： G11C16/102

    摘要： A non-volatile semiconductor memory device according to the invention includes a copy area latch circuit for latching information therein, a copy source address latch circuit for latching therein information read from a copy source, and write control means for comparing the information latched in the copy area latch circuit and the information latched in the copy source address latch circuit with each other, and automatically copying data latched in a source area of the copy source to a destination area of a copy destination, the destination area corresponding to the source area, until the information latched in the copy area latch circuit and the information latched in the copy source address latch circuit become coincide with each other following implementation of a newly provided copy command when data is copied from external storage means as a copy source to a non-volatile memory.

    摘要翻译： 根据本发明的非易失性半导体存储器件包括：用于锁存信息的复制区域锁存电路，用于锁存从复制源读取的信息的复制源地址锁存电路;以及用于将复制中锁存的信息进行比较的写入控制装置 区域锁存电路和锁存在复制源地址锁存电路中的信息，并且自动将锁存在复制源的源区域中的数据复制到复制目的地的目的地区域，对应于源区域的目的地区域，直到 锁存在复制区域锁存电路中的信息和在复制源地址锁存电路中锁存的信息在从作为复制源的外部存储装置复制到非易失性的情况下实现新提供的复制命令之后彼此重合 记忆。