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    A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device
    2.
    发明申请
    A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device 有权
    用于应变硅MOSFET器件的嵌入式多晶硅栅极结构

    公开(公告)号：US20060009001A1

    公开(公告)日：2006-01-12

    申请号：US10864952

    申请日：2004-06-10

    申请人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

    发明人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/76

    CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

    摘要： Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

    摘要翻译： 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

    CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance
    3.
    发明申请
    CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance 审中-公开
    CMOS器件具有选择性形成和回填的半导体衬底区域，以提高器件性能

    公开(公告)号：US20060118878A1

    公开(公告)日：2006-06-08

    申请号：US11003844

    申请日：2004-12-02

    申请人： Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

    发明人： Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor substrate; forming isolation regions to separate active areas comprising a PMOS device region and an NMOS device region; lithographically patterning the semiconductor substrate and etching respective recessed areas including the respective NMOS and PMOS device regions into the silicon semiconductor substrate to a predetermined depth; backfilling the respective recessed areas with at least one semiconductor alloy; and, forming gate structures and offset spacers over the respective NMOS and PMOS device regions.

    摘要翻译： 具有选择的应力水平和施加在相应沟道区上的类型的NMOS和PMOS器件对及其形成方法，所述方法包括提供半导体衬底; 形成隔离区以分离包括PMOS器件区和NMOS器件区的有源区; 将半导体衬底光刻图形化并将包括各个NMOS和PMOS器件区域的各个凹陷区域蚀刻到硅半导体衬底中至预定深度; 用至少一种半导体合金回填相应的凹陷区域; 以及在各个NMOS和PMOS器件区域上形成栅极结构和偏置间隔物。

    Metal contact structure and method of manufacture
    10.
    发明申请
    Metal contact structure and method of manufacture 审中-公开
    金属接触结构及制造方法

    公开(公告)号：US20050151166A1

    公开(公告)日：2005-07-14

    申请号：US10835100

    申请日：2004-04-29

    申请人： Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having a metal contact is provided. In the preferred embodiment, a metal contact is provided through an interlayer dielectric and is in electrical contact with a metal structure, such as a metal gate electrode of a transistor. A conductive layer is provided between the metal contact and the metal structure. The conductive layer provides one or more of a barrier layer, an adhesion layer, or an etch stop layer. The conductive layer is preferably an elemental metal, metal alloy, metal nitride, metal oxide, or a combination thereof. In an alternative embodiment, the conductive layer is formed of polysilicon.

    摘要翻译： 提供具有金属接触的半导体器件。 在优选实施例中，通过层间电介质提供金属接触，并与诸如晶体管的金属栅电极的金属结构电接触。 在金属接触件和金属结构之间设置导电层。 导电层提供阻挡层，粘合层或蚀刻停止层中的一个或多个。 导电层优选为元素金属，金属合金，金属氮化物，金属氧化物或其组合。 在替代实施例中，导电层由多晶硅形成。