公开(公告)号：US07476922B2

公开(公告)日：2009-01-13

申请号：US10969098

申请日：2004-10-20

申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

摘要： A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

摘要翻译： 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

公开(公告)号：US20060006449A1

公开(公告)日：2006-01-12

申请号：US11174954

申请日：2005-07-05

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC分类号： H01L27/108

CPC分类号： H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/65

摘要： In semiconductor integrated circuit devices having a hybrid dielectric layer and methods of fabricating the same, the hybrid dielectric layer includes a lower dielectric layer, an intermediate dielectric layer and an upper dielectric layer which are sequentially stacked. The lower dielectric layer contains hafnium (Hf) or zirconium (Zr). The upper dielectric layer also contains Hf or Zr. The intermediate dielectric layer is formed of a material layer having a voltage dependent capacitance variation lower than that of the lower dielectric layer.

摘要翻译： 在具有混合电介质层的半导体集成电路器件及其制造方法中，混合电介质层包括依次层叠的下部电介质层，中间电介质层和上部电介质层。 下介电层含有铪（Hf）或锆（Zr）。 上部介电层也含有Hf或Zr。 中间电介质层由具有相对于下电介质层的电压相关电容变化的材料层形成。

公开(公告)号：US20060014398A1

公开(公告)日：2006-01-19

申请号：US11149498

申请日：2005-06-09

申请人： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02274 ,  C23C16/405 ,  C23C16/45542 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.

摘要翻译： 使用等离子体增强原子层沉积技术形成电介质层的方法包括：将具有三维结构的半导体衬底加载到反应室中; 并重复执行以下步骤，直到形成具有所需厚度的介电层：将源气体供应到反应室中; 停止源气体的供给并清除剩余在反应室内的源气体; 并且在净化源气体之后将氧气供应到反应室中，并施加用于氧等离子体处理的RF功率，所施加的RF功率的水平和氧气的分压同时增加， 尺寸结构。

公开(公告)号：US20050087879A1

公开(公告)日：2005-04-28

申请号：US10969098

申请日：2004-10-20

申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L27/08

CPC分类号： H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

摘要： A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

摘要翻译： 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

公开(公告)号：US07166541B2

公开(公告)日：2007-01-23

申请号：US11149498

申请日：2005-06-09

申请人： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/31

CPC分类号： H01L21/02274 ,  C23C16/405 ,  C23C16/45542 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.

摘要翻译： 使用等离子体增强原子层沉积技术形成电介质层的方法包括：将具有三维结构的半导体衬底加载到反应室中; 并重复执行以下步骤，直到形成具有所需厚度的电介质层：将源气体供应到反应室中; 停止源气体的供给并清除剩余在反应室内的源气体; 并且在净化源气体之后将氧气供应到反应室中，并施加用于氧等离子体处理的RF功率，所施加的RF功率的水平和氧气的分压同时增加， 尺寸结构。

公开(公告)号：US20060078678A1

公开(公告)日：2006-04-13

申请号：US11247295

申请日：2005-10-11

申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC分类号： C23C16/00

CPC分类号： C23C16/45529 ,  C23C16/405 ,  C23C16/45542

摘要： Methods of forming a thin film by atomic layer deposition are disclosed. These methods generally include the steps of loading a substrate into a reaction chamber, and injecting a first source gas containing a first atom into the reaction chamber to form a chemical adsorption layer containing the first atom on the substrate. In one representative embodiment, a first reaction gas is then injected into the reaction chamber while a first plasma power is applied to the reaction chamber such that the first reaction gas reacts with the chemical adsorption layer containing the first atom to form a first thin film on the substrate. A second source gas containing a second atom is then injected into the reaction chamber to form a chemical adsorption layer containing the second atom on the substrate having the first thin film. A second reaction gas is next injected into the reaction chamber while a second plasma power, which is higher than the first plasma power, is applied to the reaction chamber such that the second reaction gas reacts with the chemical adsorption layer containing the second atom to form a second thin film on the substrate. The first plasma power may be a value selected in a range equal to or greater than 0 W and less than about 500 W, and the second plasma power may be a value selected in a range greater than the first plasma power and less than about 2000 W. A thickness of the second thin film may be equal to or greater than a thickness of the first thin film.

摘要翻译： 公开了通过原子层沉积形成薄膜的方法。 这些方法通常包括将衬底装载到反应室中的步骤，以及将含有第一原子的第一源气体注入到反应室中以形成在衬底上含有第一原子的化学吸附层。 在一个代表性的实施方案中，然后将第一反应气体注入到反应室中，同时将第一等离子体功率施加到反应室，使得第一反应气体与含有第一原子的化学吸附层反应以形成第一薄膜 底物。 然后将含有第二原子的第二源气体注入反应室，以形成含有第二原子的化学吸附层，该第二原子具有第一薄膜。 接着将第二反应气体注入反应室，同时将高于第一等离子体功率的第二等离子体功率施加到反应室，使得第二反应气体与含有第二原子的化学吸附层反应形成 在衬底上的第二薄膜。 第一等离子体功率可以是在等于或大于0W且小于约500W的范围内选择的值，并且第二等离子体功率可以是在大于第一等离子体功率的范围内选择的值，并且小于约2000 第二薄膜的厚度可以等于或大于第一薄膜的厚度。

公开(公告)号：US07435654B2

公开(公告)日：2008-10-14

申请号：US11452828

申请日：2006-06-14

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/20 ,  H01L21/44

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层为 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US20060234466A1

公开(公告)日：2006-10-19

申请号：US11452828

申请日：2006-06-14

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US07091548B2

公开(公告)日：2006-08-15

申请号：US10874461

申请日：2004-06-23

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US20050063141A1

公开(公告)日：2005-03-24

申请号：US10874461

申请日：2004-06-23

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L27/02 ,  H01G4/20 ,  H01L21/02 ,  H01L21/316 ,  H01L29/00

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。