公开(公告)号：US20070006451A1

公开(公告)日：2007-01-11

申请号：US11475166

申请日：2006-06-27

申请人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

发明人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

IPC分类号： H01R43/00

CPC分类号： H01L21/7685 ,  H01L21/32139 ,  Y10T29/49117

摘要： Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask. The metal wiring having at least one metal layer pattern and at least one barrier metal layer pattern may be formed on the substrate by etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask. The metal wiring having a reduced width may be obtained without a failure (e.g., a bridge).

摘要翻译： 本发明的示例性实施例涉及在半导体器件中形成金属布线的方法。 本发明的其他示例性实施例涉及在半导体器件中形成金属布线而不在相邻金属布线之间产生桥的方法。 在半导体器件中形成金属布线的方法中，可以在衬底上依次形成至少一个金属层和至少一个阻挡层。 金属阻挡层可以形成在至少一个阻挡金属层上。 可以在金属阻挡层上形成硬掩模层。 可以通过在不暴露至少一个阻挡金属层的情况下蚀刻硬掩模层而在金属阻挡层上形成硬掩模图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻金属阻挡层，可以在至少一个阻挡金属层上形成金属阻挡层图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻至少一个阻挡金属层和至少一个金属层，可以在基板上形成具有至少一个金属层图案和至少一个阻挡金属层图案的金属布线。 可以获得具有减小的宽度的金属布线而没有故障（例如桥）。

公开(公告)号：US07452807B2

公开(公告)日：2008-11-18

申请号：US11475166

申请日：2006-06-27

申请人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

发明人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

IPC分类号： H01L21/44

CPC分类号： H01L21/7685 ,  H01L21/32139 ,  Y10T29/49117

摘要： Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask. The metal wiring having at least one metal layer pattern and at least one barrier metal layer pattern may be formed on the substrate by etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask. The metal wiring having a reduced width may be obtained without a failure (e.g., a bridge).

摘要翻译： 本发明的示例性实施例涉及在半导体器件中形成金属布线的方法。 本发明的其他示例性实施例涉及在半导体器件中形成金属布线而不在相邻金属布线之间产生桥的方法。 在半导体器件中形成金属布线的方法中，可以在衬底上依次形成至少一个金属层和至少一个阻挡层。 金属阻挡层可以形成在至少一个阻挡金属层上。 可以在金属阻挡层上形成硬掩模层。 可以通过在不暴露至少一个阻挡金属层的情况下蚀刻硬掩模层而在金属阻挡层上形成硬掩模图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻金属阻挡层，可以在至少一个阻挡金属层上形成金属阻挡层图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻至少一个阻挡金属层和至少一个金属层，可以在基板上形成具有至少一个金属层图案和至少一个阻挡金属层图案的金属布线。 可以获得具有减小的宽度的金属布线而没有故障（例如桥）。

公开(公告)号：US08241512B2

公开(公告)日：2012-08-14

申请号：US12289637

申请日：2008-10-31

申请人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

发明人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

摘要： A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

摘要翻译： 形成离子注入掩模的方法包括在半导体衬底上形成场区，在半导体衬底上形成非晶碳层，在非晶碳层上形成硬掩模层，在硬掩模层上形成蚀刻掩模图案， 蚀刻硬掩模层和非晶碳层，通过蚀刻掩模图案露出场区，蚀刻硬掩模层和无定形碳层形成硬掩模层图案和无定形碳层图案。

公开(公告)号：US20090117744A1

公开(公告)日：2009-05-07

申请号：US12289637

申请日：2008-10-31

申请人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

发明人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

IPC分类号： H01L21/311

CPC分类号： H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

摘要： A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

摘要翻译： 形成离子注入掩模的方法包括在半导体衬底上形成场区，在半导体衬底上形成非晶碳层，在非晶碳层上形成硬掩模层，在硬掩模层上形成蚀刻掩模图案， 蚀刻硬掩模层和非晶碳层，通过蚀刻掩模图案露出场区，蚀刻硬掩模层和无定形碳层形成硬掩模层图案和无定形碳层图案。

公开(公告)号：US09440539B2

公开(公告)日：2016-09-13

申请号：US13418573

申请日：2012-03-13

申请人： Eun Kyu Lee ,  Yong-Woo Lee ,  Tae-Suk Kim ,  Kyoung-Min Kwon ,  Jung-Ho Yoo

发明人： Eun Kyu Lee ,  Yong-Woo Lee ,  Tae-Suk Kim ,  Kyoung-Min Kwon ,  Jung-Ho Yoo

IPC分类号： B60L1/00 ,  B60L7/16 ,  H02J7/34 ,  B60L9/00 ,  B60L11/00 ,  B60L15/00 ,  B60M3/06 ,  H02M3/158

CPC分类号： B60L1/00 ,  B60L7/16 ,  B60L9/00 ,  B60L11/005 ,  B60L15/002 ,  B60L15/007 ,  B60L2200/26 ,  B60L2210/12 ,  B60L2210/14 ,  B60L2270/147 ,  B60L2270/40 ,  B60M3/06 ,  H02J7/345 ,  H02M3/1582 ,  Y02T10/7022 ,  Y02T10/7077 ,  Y02T10/7225 ,  Y02T10/7233 ,  Y02T90/16

摘要： An energy storage apparatus has developed for railway vehicles by adopting a bidirectional DC-DC converter to increase the efficiency of charge/discharge, comprising that; a power receiving unit, filter unit, charging unit storage unit having a plurality of super-capacitors, capacitor monitoring unit, a plurality of bidirectional DC-DC converters arranged in parallel, and voltage detector electrically connected to the filter unit, current detector for detecting the currents flowing. The controller further comprises; an analog interface board, signal identifying board, signal control board, digital output contact unit, communicating board, PWM control board, optical output board, external gate driver. The PWM control board includes; a sensor input circuit, A/D converter, calculation unit, calculation control processor, and power monitoring unit. It is easy to add a storage unit including supercapacitor in a form of box module for increasing capacity and efficient of charging/discharging of the storage unit through various sensors and signal checking.

摘要翻译： 通过采用双向DC-DC转换器来增加充电/放电的效率，已经开发了用于铁路车辆的能量存储装置，包括： 电力接收单元，滤波器单元，具有多个超级电容器的充电单元存储单元，电容器监视单元，并联布置的多个双向DC-DC转换器和电连接到滤波器单元的电压检测器，用于检测的电流检测器 电流流过。 控制器还包括： 模拟接口板，信号识别板，信号控制板，数字输出接点单元，通信板，PWM控制板，光输出板，外部门驱动器。 PWM控制板包括： 传感器输入电路，A / D转换器，计算单元，计算控制处理器和电力监控单元。 通过各种传感器和信号检查，可以容易地添加一种包含超级电容器的存储单元，该电容器采用盒式模块，以通过各种传感器和信号检查提高存储单元的容量和充放电效率。

公开(公告)号：US08872752B2

公开(公告)日：2014-10-28

申请号：US13648505

申请日：2012-10-10

申请人： Sung-Man Kim ,  Bong-Jun Lee ,  Shin-Tack Kang ,  Hyeong-Jun Park ,  Yong-Woo Lee

发明人： Sung-Man Kim ,  Bong-Jun Lee ,  Shin-Tack Kang ,  Hyeong-Jun Park ,  Yong-Woo Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3614 ,  G09G2310/0248 ,  G11C19/184

摘要： A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having an output terminal electrically connected to a respective one of the plurality of gate lines. The multiple signal applying unit applies a sub scan signal and a main scan signal. The sub scan signal and the main scan signal sequentially activate each of the plurality of gate lines. Therefore, the scan lines receive the scan signal twice, so that the liquid crystal capacitors electrically connected to the gate lines receive the data voltage twice. As a result, even though the time for charging the liquid crystal capacitors may be reduced, the liquid crystal capacitors may be fully charged to enhance display quality.

摘要翻译： 扫描驱动器驱动具有传送扫描信号的多条栅极线的显示装置和传送数据信号的多条源极线。 扫描驱动器包括移位寄存器和多信号施加单元。 移位寄存器包括多个级联连接的级，每级具有电连接到多条栅极线中的相应一条栅线的输出端。 多信号施加单元施加副扫描信号和主扫描信号。 子扫描信号和主扫描信号顺序地激活多条栅极线中的每一条。 因此，扫描线接收扫描信号两次，使得电连接到栅极线的液晶电容器接收数据电压两次。 结果，即使可以减少液晶电容器的充电时间，液晶电容器也可能被充满电以提高显示质量。

公开(公告)号：US08502933B2

公开(公告)日：2013-08-06

申请号：US13084635

申请日：2011-04-12

申请人： Jin-Hee Park ,  Tae-Seok Jang ,  Seok-Won Kang ,  Yong-Woo Lee ,  Ju-Young Yoon ,  Jae-Joong Kwon ,  Seung-Hwa Ha

发明人： Jin-Hee Park ,  Tae-Seok Jang ,  Seok-Won Kang ,  Yong-Woo Lee ,  Ju-Young Yoon ,  Jae-Joong Kwon ,  Seung-Hwa Ha

IPC分类号： G02F1/1333 ,  G02F1/1335

CPC分类号： G02F1/133615 ,  G02B6/0031 ,  G02B6/0046 ,  G02B6/0073 ,  G02B6/0083 ,  G02B6/0085 ,  G02B6/0088 ,  G02F1/133308 ,  G02F2001/133314 ,  Y10T29/49002

摘要： A backlight unit includes a mold frame, a metal core printed circuit board (“MCPCB”) on which at least one light emitting diode (“LED”) is mounted, a reflector, a light guide plate, and an optical sheet. The mold frame includes an MCPCB fixing portion, the MCPCB is directly and removably disposed on the MCPCB fixing portion, and a lower surface of the MCPCB is exposed to the outside of the mold frame. On the MCPCB, a reflector, a light guide plate, and an optical sheet are placed in the order named. The light guide plate has a light entering surface facing the LED.

摘要翻译： 背光单元包括：模架，金属芯印刷电路板（“MCPCB”），其上安装有至少一个发光二极管（“LED”），反射器，导光板和光学片。 模具框架包括MCPCB固定部分，MCPCB直接并可移除地设置在MCPCB固定部分上，并且MCPCB的下表面暴露于模具框架的外部。 在MCPCB上，按照命名的顺序放置反射器，导光板和光学片。 导光板具有面向LED的光入射面。

公开(公告)号：US08199280B2

公开(公告)日：2012-06-12

申请号：US12470038

申请日：2009-05-21

申请人： Heu-Gon Kim ,  In-Sun Hwang ,  Taek-Sun Shin ,  Byung-Seo Yoon ,  Yong-Woo Lee ,  Se-Ki Park

发明人： Heu-Gon Kim ,  In-Sun Hwang ,  Taek-Sun Shin ,  Byung-Seo Yoon ,  Yong-Woo Lee ,  Se-Ki Park

IPC分类号： G02F1/1335

CPC分类号： G02B6/008 ,  G02B6/0038 ,  G02B6/0046 ,  G02B6/005 ,  G02B6/0068

摘要： A backlight assembly includes; a plurality of light guide blocks disposed substantially in parallel with each other along a first direction, each of the plurality of light guide blocks including; a light guide plate (“LGP”) having a wedge-shape decreasing in thickness from a first side thereof to a second side thereof, and a light source unit disposed facing a side surface of the LGP, and a light source driving unit which individually controls the light source units of the plurality of light guide blocks to emit light via a local dimming method.

摘要翻译： 背光组件包括： 沿着第一方向彼此大致平行地设置的多个导光块，所述多个导光块中的每一个包括： 具有从其第一侧至第二侧的厚度减小的导光板（“LGP”）以及面向LGP的侧面配置的光源单元，以及单独的光源驱动单元 控制多个导光块的光源单元通过局部调光方式发光。

公开(公告)号：US08169582B2

公开(公告)日：2012-05-01

申请号：US12775196

申请日：2010-05-06

申请人： Mee-Hye Jung ,  Chong-Chul Chai ,  Yong-Woo Lee ,  Young-Gu Kim

发明人： Mee-Hye Jung ,  Chong-Chul Chai ,  Yong-Woo Lee ,  Young-Gu Kim

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707 ,  G02F1/133788 ,  G02F1/136209 ,  G02F1/136213 ,  G02F2001/133742 ,  G02F2001/134345

摘要： A liquid crystal display includes a first substrate and a second substrate facing each other, a pixel electrode disposed on the first substrate and including a first sub-pixel electrode and a second sub-pixel electrode spaced apart from the first sub-pixel electrode by a gap, a common electrode disposed on the second substrate, a shielding member disposed on the first substrate or the second substrate and overlapping the gap between the first sub-pixel electrode and the second sub-pixel electrode, an alignment layer disposed on at least one of the pixel electrode and the common electrode, and a liquid crystal layer disposed between the first substrate and the second substrate.

摘要翻译： 液晶显示器包括第一基板和彼此面对的第二基板，设置在第一基板上并包括第一子像素电极和与第一子像素电极间隔开的第二子像素电极的像素电极， 间隙，设置在第二基板上的公共电极，设置在第一基板或第二基板上并与第一子像素电极和第二子像素电极之间的间隙重叠的屏蔽部件，配置在至少一个 的像素电极和公共电极，以及设置在第一基板和第二基板之间的液晶层。

公开(公告)号：US07847907B2

公开(公告)日：2010-12-07

申请号：US11753249

申请日：2007-05-24

申请人： In-Woo Kim ,  Dong-Gyu Kim ,  Jeong-Ho Lee ,  Young-Goo Song ,  Hyun Park ,  Min-Wook Park ,  In-Ho Park ,  Yong-Woo Lee ,  Min-Hyung Choo ,  Kyung-Suk Jung

发明人： In-Woo Kim ,  Dong-Gyu Kim ,  Jeong-Ho Lee ,  Young-Goo Song ,  Hyun Park ,  Min-Wook Park ,  In-Ho Park ,  Yong-Woo Lee ,  Min-Hyung Choo ,  Kyung-Suk Jung

IPC分类号： G02F1/1343

CPC分类号： G02F1/136259 ,  G02F2001/136236 ,  G02F2201/123

摘要： A display substrate, a method of fabricating the same, and a liquid crystal display apparatus having the same. The display substrate includes a storage electrode extending over first and second areas formed on a substrate, a insulating layer pattern formed on the storage electrode, and first and second pixel electrodes formed on the insulating layer pattern. At least one of the first and second pixel electrodes has at least one recess. The insulating layer pattern has first and second openings formed in the first and second areas corresponding to the storage electrode. Accordingly, electric short circuits between the first and second pixel electrodes is prevented due to the recess or the openings during the manufacturing process for the first and second pixel electrodes.

摘要翻译： 显示基板，其制造方法和具有该显示基板的液晶显示装置。 显示基板包括在形成在基板上的第一和第二区域上延伸的存储电极，形成在存储电极上的绝缘层图案，以及形成在绝缘层图案上的第一和第二像素电极。 第一和第二像素电极中的至少一个具有至少一个凹部。 绝缘层图案具有形成在对应于存储电极的第一和第二区域中的第一和第二开口。 因此，在第一和第二像素电极的制造过程中由于凹部或开口而防止第一和第二像素电极之间的电短路。