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    Ion implantation mask forming method
    1.
    发明授权
    Ion implantation mask forming method 有权
    离子注入掩模成型方法

    公开(公告)号：US08241512B2

    公开(公告)日：2012-08-14

    申请号：US12289637

    申请日：2008-10-31

    申请人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

    发明人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

    摘要： A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

    摘要翻译： 形成离子注入掩模的方法包括在半导体衬底上形成场区，在半导体衬底上形成非晶碳层，在非晶碳层上形成硬掩模层，在硬掩模层上形成蚀刻掩模图案， 蚀刻硬掩模层和非晶碳层，通过蚀刻掩模图案露出场区，蚀刻硬掩模层和无定形碳层形成硬掩模层图案和无定形碳层图案。

    Ion implantation mask forming method
    2.
    发明申请
    Ion implantation mask forming method 有权
    离子注入掩模成型方法

    公开(公告)号：US20090117744A1

    公开(公告)日：2009-05-07

    申请号：US12289637

    申请日：2008-10-31

    申请人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

    发明人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

    IPC分类号： H01L21/311

    CPC分类号： H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

    摘要： A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

    摘要翻译： 形成离子注入掩模的方法包括在半导体衬底上形成场区，在半导体衬底上形成非晶碳层，在非晶碳层上形成硬掩模层，在硬掩模层上形成蚀刻掩模图案， 蚀刻硬掩模层和非晶碳层，通过蚀刻掩模图案露出场区，蚀刻硬掩模层和无定形碳层形成硬掩模层图案和无定形碳层图案。

    Methods of fabricating semiconductor device including fin-fet
    3.
    发明授权
    Methods of fabricating semiconductor device including fin-fet 失效
    制造半导体器件的方法包括鳍片

    公开(公告)号：US07745290B2

    公开(公告)日：2010-06-29

    申请号：US11773372

    申请日：2007-07-03

    申请人： Jun Seo ,  Jong-Heui Song ,  Jae-Seung Hwang ,  Min-Chul Chae ,  Woo-Jin Cho ,  Yun-Seung Kang ,  Young-Mi Lee

    发明人： Jun Seo ,  Jong-Heui Song ,  Jae-Seung Hwang ,  Min-Chul Chae ,  Woo-Jin Cho ,  Yun-Seung Kang ,  Young-Mi Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/7851

    摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

    摘要翻译： 一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第 牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

    Thin layer structure and method of forming the same
    5.
    发明授权
    Thin layer structure and method of forming the same 失效
    薄层结构及其形成方法

    公开(公告)号：US07534704B2

    公开(公告)日：2009-05-19

    申请号：US11449839

    申请日：2006-06-09

    申请人： Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

    发明人： Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

    IPC分类号： H01L21/20

    CPC分类号： H01L21/84 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/76262 ,  H01L27/1203

    摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

    摘要翻译： 在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。 在第一开口中形成包括单晶硅的一种或多种初步种子图案。 在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。 通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。 第二绝缘图案包括具有平坦底部的第二开口。 在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

    Method of fabricating semiconductor device having contact hole with high aspect-ratio
    6.
    发明授权
    Method of fabricating semiconductor device having contact hole with high aspect-ratio 有权
    制造具有高纵横比的接触孔的半导体器件的方法

    公开(公告)号：US07531450B2

    公开(公告)日：2009-05-12

    申请号：US11759788

    申请日：2007-06-07

    申请人： Yun-Seung Kang ,  Jun Seo ,  Min-Chul Chae ,  Jae-Seung Hwang ,  Sung-Un Kwon ,  Woo-Jin Cho

    发明人： Yun-Seung Kang ,  Jun Seo ,  Min-Chul Chae ,  Jae-Seung Hwang ,  Sung-Un Kwon ,  Woo-Jin Cho

    IPC分类号： H01L21/44

    CPC分类号： H01L27/11551 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/0688 ,  H01L27/11526

    摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

    摘要翻译： 提供一种制造具有高纵横比的接触孔的半导体器件的方法。 该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

    Method of forming a metal wiring in a semiconductor device
    7.
    发明授权
    Method of forming a metal wiring in a semiconductor device 有权
    在半导体器件中形成金属布线的方法

    公开(公告)号：US07452807B2

    公开(公告)日：2008-11-18

    申请号：US11475166

    申请日：2006-06-27

    申请人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

    发明人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/7685 ,  H01L21/32139 ,  Y10T29/49117

    摘要： Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask. The metal wiring having at least one metal layer pattern and at least one barrier metal layer pattern may be formed on the substrate by etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask. The metal wiring having a reduced width may be obtained without a failure (e.g., a bridge).

    摘要翻译： 本发明的示例性实施例涉及在半导体器件中形成金属布线的方法。 本发明的其他示例性实施例涉及在半导体器件中形成金属布线而不在相邻金属布线之间产生桥的方法。 在半导体器件中形成金属布线的方法中，可以在衬底上依次形成至少一个金属层和至少一个阻挡层。 金属阻挡层可以形成在至少一个阻挡金属层上。 可以在金属阻挡层上形成硬掩模层。 可以通过在不暴露至少一个阻挡金属层的情况下蚀刻硬掩模层而在金属阻挡层上形成硬掩模图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻金属阻挡层，可以在至少一个阻挡金属层上形成金属阻挡层图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻至少一个阻挡金属层和至少一个金属层，可以在基板上形成具有至少一个金属层图案和至少一个阻挡金属层图案的金属布线。 可以获得具有减小的宽度的金属布线而没有故障（例如桥）。

    Method of forming a metal wiring in a semiconductor device
    8.
    发明申请
    Method of forming a metal wiring in a semiconductor device 有权
    在半导体器件中形成金属布线的方法

    公开(公告)号：US20070006451A1

    公开(公告)日：2007-01-11

    申请号：US11475166

    申请日：2006-06-27

    申请人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

    发明人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

    IPC分类号： H01R43/00

    CPC分类号： H01L21/7685 ,  H01L21/32139 ,  Y10T29/49117

    摘要： Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask. The metal wiring having at least one metal layer pattern and at least one barrier metal layer pattern may be formed on the substrate by etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask. The metal wiring having a reduced width may be obtained without a failure (e.g., a bridge).

    摘要翻译： 本发明的示例性实施例涉及在半导体器件中形成金属布线的方法。 本发明的其他示例性实施例涉及在半导体器件中形成金属布线而不在相邻金属布线之间产生桥的方法。 在半导体器件中形成金属布线的方法中，可以在衬底上依次形成至少一个金属层和至少一个阻挡层。 金属阻挡层可以形成在至少一个阻挡金属层上。 可以在金属阻挡层上形成硬掩模层。 可以通过在不暴露至少一个阻挡金属层的情况下蚀刻硬掩模层而在金属阻挡层上形成硬掩模图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻金属阻挡层，可以在至少一个阻挡金属层上形成金属阻挡层图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻至少一个阻挡金属层和至少一个金属层，可以在基板上形成具有至少一个金属层图案和至少一个阻挡金属层图案的金属布线。 可以获得具有减小的宽度的金属布线而没有故障（例如桥）。

    Phase change memory device and method of manufacturing the same
    10.
    发明申请
    Phase change memory device and method of manufacturing the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US20090090899A1

    公开(公告)日：2009-04-09

    申请号：US12285531

    申请日：2008-10-08

    申请人： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

    发明人： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

    IPC分类号： H01L45/00

    CPC分类号： H01L45/12 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.

    摘要翻译： 一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成 在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层 绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。