公开(公告)号：US08227149B2

公开(公告)日：2012-07-24

申请号：US12656881

申请日：2010-02-18

申请人： YongJin Chun ,  Soohan Choi ,  Sangwook Kim ,  Seongwoon Choi ,  Sukjoo Lee ,  Sungwoo Lee ,  Youngchang Kim ,  SungSoo Suh ,  Jin-sun Choi

发明人： YongJin Chun ,  Soohan Choi ,  Sangwook Kim ,  Seongwoon Choi ,  Sukjoo Lee ,  Sungwoo Lee ,  Youngchang Kim ,  SungSoo Suh ,  Jin-sun Choi

IPC分类号： G03F1/70

CPC分类号： G03F1/36

摘要： Methods of forming masks. According to the methods, a target pattern is set. Generation of a side lobe caused by the target pattern is verified. A preliminary target pattern and a preliminary side lobe pattern are set, in the target pattern and a region where the side lobe is generated, respectively. An interference pattern map using the preliminary target pattern and the preliminary side lobe pattern is created. At least one of regions having a phase identical or opposite to that of a position of the preliminary target pattern in the interference pattern map is set to an interference auxiliary pattern. A mask using the interference auxiliary pattern and the target pattern is formed.

摘要翻译： 形成掩模的方法 根据该方法，设定目标图案。 验证由目标图案引起的旁瓣的产生。 分别在目标图案和产生旁瓣的区域中分别设置初步目标图案和初步旁瓣图案。 创建使用初步目标图案和初步旁瓣图案的干涉图案图。 具有与干涉图案图中的预备目标图案的位置相同或相反的相位的区域中的至少一个被设置为干涉辅助图案。 形成使用干涉辅助图案和目标图案的掩模。

公开(公告)号：US20100216063A1

公开(公告)日：2010-08-26

申请号：US12656881

申请日：2010-02-18

申请人： YongJin Chun ,  Soohan Choi ,  Sangwook Kim ,  Seongwoon Choi ,  Sukjoo Lee ,  Sungwoo Lee ,  Youngchang Kim ,  SungSoo Suh ,  Jin-sun Choi

发明人： YongJin Chun ,  Soohan Choi ,  Sangwook Kim ,  Seongwoon Choi ,  Sukjoo Lee ,  Sungwoo Lee ,  Youngchang Kim ,  SungSoo Suh ,  Jin-sun Choi

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： Methods of forming masks. According to the methods, a target pattern is set. Generation of a side lobe caused by the target pattern is verified. A preliminary target pattern and a preliminary side lobe pattern are set, in the target pattern and a region where the side lobe is generated, respectively. An interference pattern map using the preliminary target pattern and the preliminary side lobe pattern is created. At least one of regions having a phase identical or opposite to that of a position of the preliminary target pattern in the interference pattern map is set to an interference auxiliary pattern. A mask using the interference auxiliary pattern and the target pattern is formed.

摘要翻译： 形成掩模的方法 根据该方法，设定目标图案。 验证由目标图案引起的旁瓣的产生。 分别在目标图案和产生旁瓣的区域中分别设置初步目标图案和初步旁瓣图案。 创建使用初步目标图案和初步旁瓣图案的干涉图案图。 具有与干涉图案图中的预备目标图案的位置相同或相反的相位的区域中的至少一个被设置为干涉辅助图案。 形成使用干涉辅助图案和目标图案的掩模。

公开(公告)号：US5308784A

公开(公告)日：1994-05-03

申请号：US955108

申请日：1992-10-01

申请人： Yungi Kim ,  Byeongyeol Kim ,  Soohan Choi

发明人： Yungi Kim ,  Byeongyeol Kim ,  Soohan Choi

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/762

CPC分类号： H01L21/3086 ,  H01L21/76224 ,  Y10S148/05

摘要： There is disclosed in the present invention a method for manufacturing a semiconductor device including an isolation region defined by trenches having different or equal widths respectively on a single semiconductor substrate comprising the steps of:forming insulating films on the semiconductor substrate and then forming an aperture on a passive region (isolation region);forming spacers of etch rate different from that of the insulating films on sidewalls of the aperture to define ring-shaped trench regions surrounding outline of active regions;forming another insulating film of etch rate different from that of the spacers on the substrate where the spacers are defined and removing the spacers by etching to expose the substrate within the etched spacers; andforming trenches on the exposed area of the substrate, forming an insulating film of equal character to that of the insulating films used at the time of the formation of the aperture to refill the trenches and forming the spacers on the sidewalls of the insulating film in the passive region, thereby forming ring-shaped trenches surrounding the outlines of the active regions to be an isolation region.

摘要翻译： 在本发明中公开了一种用于制造半导体器件的方法，该半导体器件包括在单个半导体衬底上分别具有不同宽度或相等宽度的沟槽限定的隔离区域，包括以下步骤：在半导体衬底上形成绝缘膜，然后形成孔 被动区域（隔离区域）; 形成与孔的侧壁上的绝缘膜的蚀刻速率不同的间隔物，以限定围绕有源区的轮廓的环形沟槽区; 形成另一绝缘膜，该绝缘膜的蚀刻速率不同于限定衬垫的衬底上的间隔物的蚀刻速率，并通过蚀刻去除间隔物以暴露蚀刻间隔物内的衬底; 以及在衬底的暴露区域上形成沟槽，形成与在形成孔口时使用的绝缘膜的绝缘膜相同的绝缘膜，以重新填充沟槽并在绝缘膜的侧壁上形成间隔物 从而形成围绕有源区域的轮廓的环形沟槽成为隔离区域。

公开(公告)号：US5498890A

公开(公告)日：1996-03-12

申请号：US908998

申请日：1992-07-06

申请人： Sungtae Kim ,  Soohan Choi

发明人： Sungtae Kim ,  Soohan Choi

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/1085 ,  H01L21/3144 ,  H01L27/115 ,  H01L28/40 ,  H01L29/511 ,  H01L29/94 ,  H01L21/28167 ,  H01L21/3145 ,  H01L21/3185

摘要： A semiconductor device and a manufacturing method thereof are disclpsed, the semiconductor device comprising: a first conductive layer; an oxide layer formed upon the first conductive layer; a nitride layer composed of multiple sublayers formed upon the oxide layer; another oxide layer formed upon the nitride layer in the form of multiple sublayers; and a second conductive layer formed upon the structure obtained through the preceding steps. Due to the unique feature of the nitride layer composed of multiple sublayers, the electrical characteristics of the semiconductor device according to the present invention is improved, and the nitride layer according to the present invention is widely applicable to semiconductor devices.

摘要翻译： 半导体器件及其制造方法被锯齿，该半导体器件包括：第一导电层; 形成在所述第一导电层上的氧化物层; 由形成在所述氧化物层上的多个子层构成的氮化物层; 形成在多个子层形式的氮化物层上的另一氧化物层; 以及形成在通过前述步骤获得的结构上的第二导电层。 由于由多个子层组成的氮化物层的独特特征，根据本发明的半导体器件的电特性得到改善，并且根据本发明的氮化物层可广泛应用于半导体器件。