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公开(公告)号：US20120168838A1
公开(公告)日：2012-07-05
申请号：US13419947
申请日：2012-03-14
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66984 , H01L21/823814 , H01L21/84 , H01L21/845 , H01L29/41766 , H01L29/456 , H01L29/49 , H01L29/66075
摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.
摘要翻译： 根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。
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公开(公告)号：US08026561B2
公开(公告)日：2011-09-27
申请号：US12725561
申请日：2010-03-17
IPC分类号： H01L21/02
CPC分类号： H01L43/02 , B01D53/1493 , B01D53/62 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1695 , H01L28/00 , H01L29/0843 , H01L29/0895 , H01L29/66984 , H01L43/10
摘要： A spin MOSFET includes: a first ferromagnetic layer provided on an upper face of a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on an upper face of the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower face and the upper face; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on an upper face of the second ferromagnetic layer; a third ferromagnetic layer provided on an upper face of the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.
摘要翻译： 自旋MOSFET包括：设置在半导体衬底的上表面上并且具有与膜平面垂直的固定磁化方向的第一铁磁层; 设置在所述第一铁磁层的上表面上的半导体层，包括与所述第一铁磁层的上表面相对的下表面，与所述下表面相对的上表面，以及与所述下表面和所述上表面不同的侧面 ; 第二铁磁层，设置在所述半导体层的上表面上，并且具有与膜平面垂直的可变磁化方向; 设置在所述第二铁磁层的上表面上的第一隧道势垒; 设置在所述第一隧道屏障的上表面上的第三铁磁层; 设置在所述半导体层的侧面上的栅极绝缘膜; 以及设置在半导体层的侧面上的栅电极，其间插入有栅极绝缘膜。
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公开(公告)号：US09112139B2
公开(公告)日：2015-08-18
申请号：US13526007
申请日：2012-06-18
申请人： Tomoaki Inokuchi , Takao Marukame , Tetsufumi Tanamoto , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito
发明人： Tomoaki Inokuchi , Takao Marukame , Tetsufumi Tanamoto , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito
CPC分类号： H01L43/08 , H01L29/66984
摘要： A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.
摘要翻译： 根据实施例的自旋晶体管包括：形成在衬底上并用作源极和漏极之一的第一磁性层; 绝缘膜，其具有面向第一磁性层的上表面的下表面，与下表面相对的上表面，以及不同于下表面和上表面的侧面，绝缘膜形成在第一磁性层的上表面上 第一磁性层，作为通道; 第二磁性层，形成在绝缘膜的上表面上并用作源极和漏极中的另一个; 沿绝缘膜的侧面形成的栅电极; 以及位于绝缘膜的栅极和侧面之间的栅极绝缘膜。
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公开(公告)号：US08373437B2
公开(公告)日：2013-02-12
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译： 根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。
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公开(公告)号：US08357962B2
公开(公告)日：2013-01-22
申请号：US12700767
申请日：2010-02-05
IPC分类号： H01L21/336
CPC分类号： H01L29/66984 , B82Y25/00 , B82Y40/00 , H01F1/405 , H01F10/1936 , H01F10/3254 , H01F41/307 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/47
摘要： A spin transistor includes a source electrode, a drain electrode, and a gate electrode on a semiconductor substrate. At least one of the source electrode and the drain electrode includes a semiconductor region and a magnetic layer. The semiconductor region is formed in the semiconductor substrate. The magnetic layer is formed on the semiconductor region, and contains a crystalline Heusler alloy containing at least one of cobalt (Co) and iron (Fe). The semiconductor region and the magnetic layer contain the same impurity element.
摘要翻译： 自旋晶体管包括在半导体衬底上的源电极，漏电极和栅电极。 源电极和漏电极中的至少一个包括半导体区域和磁性层。 半导体区域形成在半导体衬底中。 磁性层形成在半导体区域上，并含有包含钴（Co）和铁（Fe）中的至少一种的结晶Heusler合金。 半导体区域和磁性层含有相同的杂质元素。
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公开(公告)号：US20120119274A1
公开(公告)日：2012-05-17
申请号：US13360904
申请日：2012-01-30
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H01L27/22
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。
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公开(公告)号：US20120019283A1
公开(公告)日：2012-01-26
申请号：US13228852
申请日：2011-09-09
IPC分类号： H03K19/173 , H01L29/82
CPC分类号： H01L43/02 , B01D53/1493 , B01D53/62 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1695 , H01L28/00 , H01L29/0843 , H01L29/0895 , H01L29/66984 , H01L43/10
摘要： A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.
摘要翻译： 自旋MOSFET包括：设置在半导体衬底上并具有与膜平面垂直的固定磁化方向的第一铁磁层; 设置在所述第一铁磁层上的半导体层，包括与所述第一铁磁层的上表面相对的下表面，与所述下表面相对的上表面，以及与所述下表面和所述上表面不同的侧面; 第二铁磁层，设置在所述半导体层的上表面上，并且具有与膜平面垂直的可变磁化方向; 设置在第二铁磁层上的第一隧道势垒; 设置在第一隧道屏障上的第三铁磁层; 设置在所述半导体层的侧面上的栅极绝缘膜; 以及设置在半导体层的侧面上的栅电极，其间插入有栅极绝缘膜。
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8.发明授权Stack having Heusler alloy, magnetoresistive element and spin transistor using the stack, and method of manufacturing the same 有权具有Heusler合金，磁阻元件和使用该堆叠的自旋晶体管的堆叠及其制造方法公开(公告)号：US07973351B2
公开(公告)日：2011-07-05
申请号：US12565303
申请日：2009-09-23
IPC分类号： H01L21/02
CPC分类号： H01L29/66984 , H01F10/1936 , H01F10/265 , H01L27/228 , H01L43/10 , H01L43/12 , Y10T428/12611
摘要： A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.
摘要翻译： 堆叠包括结晶MgO层，结晶Heusler合金层和非晶Heusler合金层。 结晶Heusler合金层设置在MgO层上。 非晶Heusler合金层设置在结晶Heusler合金层上。
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9.发明授权Pass transistor circuit with memory function, and switching box circuit including the pass transistor circuit 有权具有存储功能的晶体管电路，以及包括传输晶体管电路的开关盒电路公开(公告)号：US08405443B2
公开(公告)日：2013-03-26
申请号：US13419555
申请日：2012-03-14
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K17/687
CPC分类号： H01L27/112 , H03K19/17736
摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
摘要翻译： 根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端 终奌站。 第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。
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10.发明申请PASS TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, AND SWITCHING BOX CIRCUIT INCLUDING THE PASS TRANSISTOR CIRCUIT 有权具有存储器功能的通用晶体管电路，以及包括通过晶体管电路的开关盒电路公开(公告)号：US20120223762A1
公开(公告)日：2012-09-06
申请号：US13419555
申请日：2012-03-14
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K17/00
CPC分类号： H01L27/112 , H03K19/17736
摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
摘要翻译： 根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端 终奌站。 第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。
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