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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07995369B2

    公开(公告)日：2011-08-09

    申请号：US12332595

    申请日：2008-12-11

    申请人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

    发明人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

    IPC分类号： G11C17/00

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/1203

    摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

    摘要翻译： 本公开涉及包括位线的半导体存储器件; 字线 布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是半导体层指向字线和位线的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘， 其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20090152610A1

    公开(公告)日：2009-06-18

    申请号：US12332595

    申请日：2008-12-11

    申请人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

    发明人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

    IPC分类号： H01L29/78

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/1203

    摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

    摘要翻译： 本公开涉及包括位线的半导体存储器件; 字线 布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是指向字线和位线的半导体层的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘， 其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

    Semiconductor memory device and manufacturing method thereof
    3.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US07977738B2

    公开(公告)日：2011-07-12

    申请号：US12497010

    申请日：2009-07-02

    申请人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

    发明人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/1022 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

    摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07154151B2

    公开(公告)日：2006-12-26

    申请号：US11015036

    申请日：2004-12-20

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0255 ,  H01L27/1203 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.

    摘要翻译： 半导体器件包括半导体衬底; 设置在半导体基板上的嵌入式绝缘层; 设置在所述嵌入绝缘层上的半导体层; 包括形成在所述半导体层内的第一导电类型源极层，形成在所述半导体层中的第一导电类型漏极层和所述源极层与所述漏极层之间的沟道形成区域的晶体管; 以及包括第二导电型第一扩散层和第一导电型第二扩散层的嵌入式绝缘层保护二极管，所述第一扩散层与所述沟道形成区域正下方的半导体衬底区域处于相同的电位，所述第二扩散层为 与第一扩散层相邻并且电连接到源极层，漏极层和沟道形成区域中的至少一个。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20080237681A1

    公开(公告)日：2008-10-02

    申请号：US12051053

    申请日：2008-03-19

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897

    摘要： This disclosure concerns a semiconductor device comprising: a bulk substrate; an insulation layer provided on the bulk substrate; a semiconductor layer containing an active area on which a semiconductor element is formed, and a dummy active area isolated from the active area and not formed with a semiconductor element thereon, the semiconductor layer being provided on the insulation layer; and a supporting unit provided beneath the dummy active area to reach the bulk substrate piercing through the insulation layer, the supporting unit supporting the dummy active area.

    摘要翻译： 本公开涉及一种半导体器件，包括：体基板; 设置在本体基板上的绝缘层; 包含其上形成有半导体元件的有源区的半导体层和与有源区隔离而不在其上形成有半导体元件的虚设有源区，所述半导体层设置在所述绝缘层上; 以及支撑单元，其设置在所述虚拟有源区域下方以到达穿过所述绝缘层的所述主体基板，所述支撑单元支撑所述虚拟有效区域。

    Semiconductor memory device and method of fabricating the same
    7.
    发明申请
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20060113686A1

    公开(公告)日：2006-06-01

    申请号：US11041250

    申请日：2005-01-25

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： H01L31/109

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841 ,  Y10S257/90

    摘要： A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with cell transistors disposed in such a manner that each of source and drain layers is shared by adjacent two cell transistors arranged in a direction, the cell transistor having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body; and logic transistors formed on the semiconductor device base to constitute a peripheral circuit of said cell array, wherein at least a part of source and drain layers of each the cell transistor is formed with a thickness different from source and drain layers of the logic transistors.

    摘要翻译： 半导体存储器件包括：半导体器件基底，具有绝缘基底和覆盖其上的半导体层; 形成在半导体器件基底上的单元阵列，其中单元晶体管以这样的方式设置，使得源极和漏极层中的每一个由在一个方向上排列的相邻的两个单元晶体管共享，该单元晶体管具有电浮动沟道体，以存储由 通道体的载体积聚状态; 以及形成在所述半导体器件基底上的逻辑晶体管，以构成所述单元阵列的外围电路，其中每个所述单元晶体管的源极和漏极层的至少一部分形成为具有与所述逻辑晶体管的源极和漏极层不同的厚度。