公开(公告)号：US20100165701A1

公开(公告)日：2010-07-01

申请号：US12536341

申请日：2009-08-05

申请人： Yoshihiro UEDA ,  Kenji TSUCHIDA ,  Kiyotaro ITAGAKI

发明人： Yoshihiro UEDA ,  Kenji TSUCHIDA ,  Kiyotaro ITAGAKI

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/10

CPC分类号： G11C13/00 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C2013/0054 ,  G11C2213/79

摘要： A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

摘要翻译： 电阻存储器包括多个存储单元，具有相互不同的电阻值的多个参考单元，至少一个读出放大器，其具有连接到从多个存储单元中选择的一个选定存储单元的第一输入端， 读取，以及连接到在读取时从多个参考单元中选择的一个选择的参考单元的第二输入端子，以及保持所述至少一个读出放大器的偏移信息的一个锁存电路。 电阻存储器还包括解码器，其根据偏移信息从多个参考单元中选择一个选定的参考单元，并将所选择的一个参考单元连接到至少一个读出放大器的第二输入端。

公开(公告)号：US20090190391A1

公开(公告)日：2009-07-30

申请号：US12356722

申请日：2009-01-21

申请人： Kiyotaro ITAGAKI ,  Yoshihiro UEDA

发明人： Kiyotaro ITAGAKI ,  Yoshihiro UEDA

IPC分类号： G11C11/02 ,  G11C11/416 ,  G11C8/08

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.

摘要翻译： 字线电压被施加到多个字线。 读/写电压施加到多个位线。 读/写电压被施加到多条源极线。 字线选择器选择字线并施加字线电压。 驱动器将预定电压施加到位线和源极线，从而向存储器单元提供电流。 读取电路读取已经流过存储器单元的第一电流，并且确定存储在存储单元中的数据。 当执行读取时，驱动器向与第一电流流过的第一位线相邻的其它位线中的第二位线提供第二电流。 第二电流在抑制要从其读取数据的存储单元中的写入错误的方向上产生磁场。

公开(公告)号：US20120320698A1

公开(公告)日：2012-12-20

申请号：US13493370

申请日：2012-06-11

申请人： Kiyotaro ITAGAKI ,  Kunihiro YAMADA ,  Yoshihisa IWATA

发明人： Kiyotaro ITAGAKI ,  Kunihiro YAMADA ,  Yoshihisa IWATA

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C2213/71 ,  H01L27/11582 ,  H01L29/7926

摘要： A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

摘要翻译： 控制电路被配置为将连接到所选择的存储器串的漏极侧选择晶体管和源极侧选择晶体管设置为非导通状态。 控制电路被配置为对连接到所选择的存储器串中未选择的存储器单元的栅极的未选择字线施加第一电压。 控制电路被配置为对连接到所选择的存储器串中所选择的存储器单元的栅极的选定字线施加第二电压。 在擦除操作中第二电压小于第一电压。

公开(公告)号：US20120307557A1

公开(公告)日：2012-12-06

申请号：US13483610

申请日：2012-05-30

申请人： Kiyotaro ITAGAKI

发明人： Kiyotaro ITAGAKI

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32

摘要： A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.

摘要翻译： 根据一个方面的非易失性半导体存储器件包括半导体衬底，存储单元阵列，存储器串，漏极侧选择晶体管，源极侧选择晶体管，字线，位线，源极线，漏极侧选择栅极线， 源极选择栅极线和控制电路。 控制电路对所选择的位线施加第一电压，从而对连接到所选位线的所选择的存储器串执行擦除操作，并且控制电路将第二电压施加到未选择的位线，从而禁止擦除 连接到未选位线的所选存储器串的操作。 第一电压大于第二电压。

公开(公告)号：US20120218821A1

公开(公告)日：2012-08-30

申请号：US13463889

申请日：2012-05-04

申请人： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

发明人： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US20120069663A1

公开(公告)日：2012-03-22

申请号：US13235389

申请日：2011-09-18

申请人： Kiyotaro ITAGAKI ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

发明人： Kiyotaro ITAGAKI ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/344 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

摘要翻译： 控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。 在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为 第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

公开(公告)号：US20110069552A1

公开(公告)日：2011-03-24

申请号：US12684349

申请日：2010-01-08

申请人： Kiyotaro ITAGAKI ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

发明人： Kiyotaro ITAGAKI ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

IPC分类号： G11C16/04

CPC分类号： H01L27/11578 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from among the plurality of memory strings. During the read operation, the control circuit is configured to apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation.

摘要翻译： 非易失性半导体存储器件包括：具有多个存储器串的存储单元阵列，每个存储器串均具有串联连接的多个存储器单元; 以及控制电路，被配置为执行用于从所述多个存储器串中的所选择的存储器串中包括的存储单元读取数据的读取操作。 在读取操作期间，控制电路被配置为将第一电压施加到不经过读取操作的未选择的存储器串中的至少一个存储器单元的栅极，并施加低于第一电压的第二电压 到没有进行读取操作的未选择的存储器串中的另一个存储器单元的门。