公开(公告)号：US20110175159A1

公开(公告)日：2011-07-21

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US07759255B2

公开(公告)日：2010-07-20

申请号：US11561700

申请日：2006-11-20

申请人： Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/8239

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

摘要： In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.

摘要翻译： 在本发明的一个实施例中，一种制造半导体器件的方法包括：在半导体衬底上形成被去除层; 在被去除层上形成半导体层; 在SOI区域中形成穿过所述半导体层到所述被去除层的沟槽; 通过使用沟槽去除待去除的层并产生空腔; 以及在所述空腔中形成绝缘膜。

公开(公告)号：US20100096682A1

公开(公告)日：2010-04-22

申请号：US12556242

申请日：2009-09-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

摘要翻译： 非易失性半导体存储装置具有串联连接的多个电可重写存储单元的存储串。 非挥发性半导体存储装置还具有形成为相对于基板向上突出的突出层。 存储器串包括：层叠在基板上的多个第一导电层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷存储层，并且能够存储电荷。 多个第一导电层中的每一个包括：平行于基板延伸的底部; 以及沿底部的突出层相对于基板向上延伸的侧部。 该突出层在平行于基板的第一方向上的宽度小于或等于其在层叠方向上的长度。

公开(公告)号：US07609551B2

公开(公告)日：2009-10-27

申请号：US11860956

申请日：2007-09-25

申请人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C11/404 ,  G11C11/4074 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42344 ,  H01L29/785 ,  H01L29/78648

摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

摘要翻译： 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

公开(公告)号：US20090212350A1

公开(公告)日：2009-08-27

申请号：US12389856

申请日：2009-02-20

申请人： Masaru KIDOH ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Akihiro Nitayama ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Masaru KIDOH ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Akihiro Nitayama ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.

摘要翻译： 非易失性半导体存储装置具有串联连接多个电可重写存储单元的多个存储串。 存储器串具有在垂直于衬底的方向上延伸的柱状半导体层; 形成为与柱状半导体层配合地夹着电荷存储层的导电层; 以及形成为与导电层的顶面接触的金属层。

公开(公告)号：US20070215943A1

公开(公告)日：2007-09-20

申请号：US11561700

申请日：2006-11-20

申请人： Takeshi HAMAMOTO ,  Akihiro Nitayama

发明人： Takeshi HAMAMOTO ,  Akihiro Nitayama

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

摘要： In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity

摘要翻译： 在本发明的一个实施例中，一种制造半导体器件的方法包括：在半导体衬底上形成被去除层; 在被去除层上形成半导体层; 在SOI区域中形成穿过所述半导体层到所述被去除层的沟槽; 通过使用沟槽去除待去除的层并产生空腔; 以及在所述空腔中形成绝缘膜

公开(公告)号：US06707706B2

公开(公告)日：2004-03-16

申请号：US10183156

申请日：2002-06-28

申请人： Akihiro Nitayama ,  Katsuhiko Hieda

发明人： Akihiro Nitayama ,  Katsuhiko Hieda

IPC分类号： G11C1124

CPC分类号： H01L27/10876 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L28/90

摘要： A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.

摘要翻译： 半导体存储器件包括形成在半导体衬底上的存储单元阵列区域中的多个柱状部分。 柱状部分通过多个沟槽彼此隔离，并且这些沟槽具有深度不同的第一和第二底部。 半导体器件包括多个单元晶体管，其包括形成在第一底部的第一扩散层区域，其比第二底部浅，形成在柱状部分的表面部分中的第二扩散层区域和多个栅电极 邻近第一和第二扩散层区域并且沿着柱状部分的至少一个侧表面部分延伸。

公开(公告)号：US5747844A

公开(公告)日：1998-05-05

申请号：US736279

申请日：1996-10-24

申请人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10882 ,  Y10S257/907

摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

公开(公告)号：US5350708A

公开(公告)日：1994-09-27

申请号：US77744

申请日：1993-06-18

申请人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10841 ,  H01L27/10823

摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

摘要翻译： 在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。 在槽的中心部分形成场氧化膜。 在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。 用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元 阵列是结构化的

公开(公告)号：US5049957A

公开(公告)日：1991-09-17

申请号：US528086

申请日：1990-05-24

申请人： Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Fumio Horiguchi

发明人： Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Fumio Horiguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： In a semiconductor memory device, a storage node electrode having a cavity is provided such that the inner surface of a storage node electrode is used as a capacitor electrode. In a DRAM fabricating method, a storage node electrode having a cavity is formed by laminating a first conductor layer, an insulating film and a second conductor layer, which in turn are patterned into a desired shape, depositing a third conductor layer on the three-layer pattern, performing anisotropic etching so as to cause the third conductor layer to remain only on the side walls of the pattern to thereby form a box-shaped conductor, forming an opening in a part of the box-shaped conductor, removing the insulating film by an etching to thereby form a cavity.

摘要翻译： 在半导体存储器件中，具有空腔的存储节点电极被设置为使得存储节点电极的内表面用作电容器电极。 在DRAM制造方法中，通过层叠第一导体层，绝缘膜和第二导体层来形成具有空腔的存储节点电极，第一导体层，绝缘膜和第二导体层又被图案化成所需形状， 层状图案，进行各向异性蚀刻，以使第三导体层仅保留在图案的侧壁上，从而形成盒状导体，在盒状导体的一部分中形成开口，去除绝缘膜 通过蚀刻从而形成空腔。