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公开(公告)号：US6121786A
公开(公告)日：2000-09-19
申请号：US106150
申请日：1998-06-29
IPC分类号： H01L27/04 , G01R31/30 , H01L21/822 , G01R31/28
CPC分类号： G01R31/30 , G01R31/3004
摘要： A semiconductor integrated circuit including an internal voltage step down circuit exhibits a first voltage characteristic I having substantially no dependence on an external power supply voltage VEXT and holding an internal power supply voltage VINT at a constant voltage VA if the external power supply voltage VEXT is in the range between two predetermined values V1 and V2. On and after the external power supply voltage VEXT exceeds the predetermined value V2, the circuit exhibits a second voltage characteristic II, in which the internal power supply voltage VINT varies from the constant voltage VA in accordance with the external power supply voltage VEXT, during a non-accelerated test (operation margin certification test). On the other hand, during the accelerated test, the circuit exhibits a third voltage characteristic III in which the internal power supply voltage VINT reaches a certain voltage VB (>VA) and goes on increasing from VB in accordance with the external power supply voltage VEXT. Thus, during the operation margin certification test, the internal power supply voltage VINT exhibits continuously varying characteristics I and II and the operation of the circuit can be assured in the voltage range from VA to VB. During the accelerated test, a voltage can be increased at a sufficiently high rate owing to the characteristic III.
摘要翻译： 包括内部降压电路的半导体集成电路如果外部电源电压VEXT处于恒定电压VA时，表现出基本上不依赖于外部电源电压VEXT的第一电压特性I和保持恒定电压VA的内部电源电压VINT 两个预定值V1和V2之间的范围。 在外部电源电压VEXT超过预定值V2之后，电路呈现第二电压特性II，其中内部电源电压VINT根据外部电源电压VEXT从恒定电压VA变化 非加速测试（操作保证金认证测试）。 另一方面，在加速试验中，电路呈现第三电压特性III，其中内部电源电压VINT达到一定电压VB（> VA），并根据外部电源电压VEXT从VB继续增加 。 因此，在运行余量验证测试期间，内部电源电压VINT呈现连续变化的特性I和II，并且可以在从VA到VB的电压范围内确保电路的操作。 在加速测试期间，由于特性III，可以以足够高的速率增加电压。
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公开(公告)号：US06937532B2
公开(公告)日：2005-08-30
申请号：US10628168
申请日：2003-07-28
IPC分类号： G11C11/413 , G11C5/02 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L27/11 , G11C7/00
摘要： A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.
摘要翻译： 半导体存储器包括存储单元阵列，冗余修复信号发生器和行解码器。 存储单元阵列包括多个存储单元行和至少一个冗余存储单元行。 冗余修复信号发生器产生指示有缺陷的存储器单元行的地址的冗余修复信号。 行解码器接收指示包括要访问的存储单元的存储单元行的行地址信号，并根据由冗余修复信号发生器产生的冗余修复信号选择冗余存储单元行。 冗余修复信号发生器位于与行解码器相对的位置，存储单元阵列位于它们之间。 这种构造可以实现自由空间的减小，从而减少面积损耗。
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公开(公告)号：US08164938B2
公开(公告)日：2012-04-24
申请号：US12942627
申请日：2010-11-09
申请人： Naoki Kuroda , Yoshinobu Yamagami
发明人： Naoki Kuroda , Yoshinobu Yamagami
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C8/16
摘要： A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.
摘要翻译： 半导体存储器件包括第一反相器和第二反相器，每个具有输入和输出，第一和第二反相器的每一个的输出连接到另一个的输入，以便存储数据; CMOS开关，被配置为连接 第一反相器的输入和写入位线，具有连接到第一反相器的输出的栅极的读取MOS晶体管和被配置为将读取的MOS晶体管连接到读取位线的MOS开关。 第一和第二逆变器具有不同的尺寸并连接到不同的源电源。
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公开(公告)号：US07817460B2
公开(公告)日：2010-10-19
申请号：US12503523
申请日：2009-07-15
申请人： Yoshinobu Yamagami
发明人： Yoshinobu Yamagami
CPC分类号： G11C5/14 , G11C11/413
摘要： A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in case where the cell power supply voltage in supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.
摘要翻译： 一种具有包括触发器的存储单元的半导体存储器件; 以及用于向存储单元提供低电压单元电源电压的存储单元电源电路。 存储单元电源电路在第一周期中提供单元电源电压，并在第二周期中提供不同单元电源电压，在以数据读周期提供单元电源电压的情况下提供预定的第一电源电压，以及 在数据被写入存储单元的情况下，在写入周期中数据未被写入到单元电源电压被提供的存储单元的情况下，以及高于第一电源电压的第二电源电压 单元电源电压在写周期中被提供给单元电源电压。
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公开(公告)号：US07778075B2
公开(公告)日：2010-08-17
申请号：US12425018
申请日：2009-04-16
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US07542368B2
公开(公告)日：2009-06-02
申请号：US11634110
申请日：2006-12-06
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US07301840B2
公开(公告)日：2007-11-27
申请号：US11266408
申请日：2005-11-04
申请人： Yoshinobu Yamagami
发明人： Yoshinobu Yamagami
IPC分类号： G11C7/02
CPC分类号： G11C11/412 , G11C11/413
摘要： There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell 1 and a dummy memory cell 1a are controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell 1a. The dummy memory cell 1a and peripheral circuitry are designed so that write time required for the dummy memory cell 1a is more than or equal to a maximum of write time required for the memory cells 1.
摘要翻译： 提供了一种半导体存储器件，其保证对所有存储器单元的写入，而不管由制造误差等引起的存储器单元的性质的波动，并且可以减少写入操作时间和功耗。 基于写放大器控制信号WAE来控制存储单元1和虚设存储单元1a的写操作。 基于指示虚拟存储单元1a的存储状态的写入完成信号WRST来确定写入操作结束定时。 伪存储单元1a和外围电路被设计成使得空存储单元1a所需的写入时间大于或等于存储单元1所需的写入时间的最大值。
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公开(公告)号：US20050047220A1
公开(公告)日：2005-03-03
申请号：US10917308
申请日：2004-08-13
申请人： Yoshinobu Yamagami
发明人： Yoshinobu Yamagami
IPC分类号： G11C11/417 , G11C11/419 , G11C11/34
CPC分类号： G11C11/419
摘要： A semiconductor memory device includes word lines, bit line pairs, memory cells 1, bit line precharge circuits 2, and write amplifiers 3, as well as a dummy word line, a dummy bit line pair, dummy memory cells 1a, 1b, and 1c, and a memory cell storing node detection circuit 6. Through the action of the dummy memory cells 1b and 1c, it is ensured that the write timing for the dummy memory cell 1a is substantially identical to the write timing for the memory cells 1. Based on changes in the states of storing nodes S1 and S2 included in the dummy memory cell 1a, the memory cell storing node detection circuit 6 generates a write completion signal WRST. As a result, a semiconductor memory device having an optimized write timing and low power consumption is provided.
摘要翻译： 半导体存储器件包括字线，位线对，存储单元1，位线预充电电路2和写放大器3，以及虚拟字线，虚拟位线对，虚拟存储单元1a，1b和1c 以及存储单元存储节点检测电路6.通过虚拟存储单元1b和1c的动作，确保虚拟存储单元1a的写入定时与存储单元1的写入定时基本相同。基于 在存储单元存储单元1a中包含的存储节点S1和S2的状态的变化中，存储单元存储节点检测电路6生成写入完成信号WRST。 结果，提供了具有优化的写入定时和低功耗的半导体存储器件。
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公开(公告)号：US08077530B2
公开(公告)日：2011-12-13
申请号：US13084026
申请日：2011-04-11
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US20100277991A1
公开(公告)日：2010-11-04
申请号：US12838119
申请日：2010-07-16
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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