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公开(公告)号：US07782865B2
公开(公告)日：2010-08-24
申请号：US11131207
申请日：2005-05-18
申请人： Yoshinori Rokugo , Hiroyuki Kikuchi
发明人： Yoshinori Rokugo , Hiroyuki Kikuchi
CPC分类号： H04L12/5601 , H04L2012/5614 , H04L2012/5616
摘要： To provide a method and network system, wherein the proper VPI values are allocated, after the user devices are connected with the network device. A user device transmits a first specific ATM cell, while a network device receives the first specific ATM cell and transmits toward the user device a second specific ATM cell which carries a proper VPI value in the information field of ATM cell. The proper VPI value in the second specific ATM cell is memorized and used by the user device for its own VPI value for communication.
摘要翻译： 提供一种方法和网络系统，其中在用户设备与网络设备连接之后分配适当的VPI值。 用户设备发送第一特定ATM信元，而网络设备接收第一特定ATM信元并向用户设备发送在ATM信元的信息字段中携带适当VPI值的第二特定ATM信元。 第二特定ATM信元中适当的VPI值由用户设备存储并由其自身的VPI值用于通信。
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公开(公告)号：US20050207422A1
公开(公告)日：2005-09-22
申请号：US11131207
申请日：2005-05-18
申请人： Yoshinori Rokugo , Hiroyuki Kikuchi
发明人： Yoshinori Rokugo , Hiroyuki Kikuchi
CPC分类号： H04L12/5601 , H04L2012/5614 , H04L2012/5616
摘要： To provide a method and network system, wherein the proper VPI values are allocated, after the user devices are connected with the network device. A user device transmits a first specific ATM cell, while a network device receives the first specific ATM cell and transmits toward the user device a second specific ATM cell which carries a proper VPI value in the information field of ATM cell. The proper VPI value in the second specific ATM cell is memorized and used by the user device for its own VPI value for communication.
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公开(公告)号：US06934291B1
公开(公告)日：2005-08-23
申请号：US09506366
申请日：2000-02-18
申请人： Yoshinori Rokugo , Hiroyuki Kikuchi
发明人： Yoshinori Rokugo , Hiroyuki Kikuchi
CPC分类号： H04L12/5601 , H04L2012/5614 , H04L2012/5616
摘要： To provide a method and network system, wherein the proper VPI values are allocated, after the user devices are connected with the network device. A user device transmits a first specific ATM cell, while a network device receives the first specific ATM cell and transmits toward the user device a second specific ATM cell which carries a proper VPI value in the information field of ATM cell. The proper VPI value in the second specific ATM cell is memorized and used by the user device for its own VPI value for communication.
摘要翻译： 提供一种方法和网络系统，其中在用户设备与网络设备连接之后分配适当的VPI值。 用户设备发送第一特定ATM信元，而网络设备接收第一特定ATM信元并向用户设备发送在ATM信元的信息字段中携带适当VPI值的第二特定ATM信元。 第二特定ATM信元中适当的VPI值由用户设备存储并由其自身的VPI值用于通信。
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公开(公告)号：US4397017A
公开(公告)日：1983-08-02
申请号：US239865
申请日：1981-03-02
申请人： Yoshinori Rokugo
发明人： Yoshinori Rokugo
IPC分类号： H04J3/07
CPC分类号： H04J3/073
摘要： It has now been confirmed as regards a stuff (justification) synchronization device for each of plesiochronous input pulse sequence to be time division multiplexed that a low frequency jitter component appears in a synchronous output pulse sequence from the effect of sampling phase lags of read pulse sequences for reading the output pulse sequence for stuffing from an elastic memory (36) of the device relative to write pulse sequences for storing the input pulse sequence in the memory at a sampling interval equal to the memory capacity. The jitter is reduced (1) by selecting a prime number, preferably thirteen and more preferably seventeen or nineteen, as the memory capacity, (2) by cyclically using selected write and read pulse sequences for phase lag monitoring, or (3) by rendering the sampling interval either random or equivalently random.
摘要翻译： 现在已经确定了用于每个准同步输入脉冲序列的填充（对齐）同步装置，以进行时分复用，使得低频抖动分量出现在同步输出脉冲序列中，从读取脉冲序列的采样相位滞后的效果 用于从相对于存储器容量的采样间隔的用于将输入脉冲序列存储在存储器中的写入脉冲序列读取用于从器件的弹性存储器（36）填充的输出脉冲序列。 通过选择素数（优选十三个，更优选十七或十九个）作为存储器容量，（2）通过循环地使用选择的写入和读取脉冲序列进行相位滞后监视来减少抖动（1），或（3）通过渲染 采样间隔随机或等效随机。
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5.发明授权Higher-order multiplex digital communication system with identification patterns specific to lower-order multiplex digital signals 失效具有特定于低阶多路复用数字信号的识别模式的高阶多路复用数字通信系统
公开(公告)号：US4727542A
公开(公告)日：1988-02-23
申请号：US22612
申请日：1987-03-04
申请人： Yoshinori Rokugo , Hiroshi Asano
发明人： Yoshinori Rokugo , Hiroshi Asano
CPC分类号： H04J3/047 , H04J3/0605 , H04J3/0685
摘要： On multiplexing a predetermined number of lower-order multiplex digital transmission signals of a common frame period into a higher-order multiplex digital communication signal, an identification pattern (X, Y, Z) is inserted in each frame of each transmission signal. The identification patterns are specific to the respective transmission signals. The identification patterns in each frame period of the respective transmission signals are multiplexed into a single pattern (I1x, I2x, I3x, I1y, I2y, I3y, I1z, I2z, I3z) in the communication signal and used to indicate lower-order multiplex digital signal receivers to which the respective transmission signals should be directed. After the communication signal is demultiplexed into lower-order multiplex digital reception signals, the identification patterns are detected with frame synchronism established between the lower-order transmission and reception signals. Each identification pattern may consist of a preselected number of binary bits where two to the power of the preselected number should not be less than the predetermined number.
摘要翻译： 在将预定数量的公共帧周期的低阶多路复用数字传输信号复用成高阶多路复用数字通信信号时，在每个发送信号的每个帧中插入识别图案（X，Y，Z）。 识别图案是针对各个传输信号的。 各个发送信号的每个帧周期中的识别模式被多路复用为通信信号中的单个模式（I1x，I2x，I3x，I1y，I2y，I3y，I1z，I2z，I3z），并用于指示低阶多路复用数字 各个传输信号应该被引导到的信号接收机。 在将通信信号解复用为低阶多路复用数字接收信号之后，利用在低级发送和接收信号之间建立的帧同步来检测识别模式。 每个识别图案可以由预选数量的二进制位组成，其中两个到预选数字的功率不应小于预定数量。
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6.发明授权Digital phase synchronous circuit and data receiving circuit including the same 失效数字相位同步电路和数据接收电路包括相同的
公开(公告)号：US5715286A
公开(公告)日：1998-02-03
申请号：US655983
申请日：1996-05-31
申请人： Masaaki Itoh , Yoshinori Rokugo
发明人： Masaaki Itoh , Yoshinori Rokugo
CPC分类号： H04J3/076 , H03L7/0993 , H03L7/143
摘要： A digital phase synchronous circuit includes a phase comparing circuit for outputting a count value according to the result of a phase comparison between an output signal and an externally input reference signal; a frequency regulating circuit for inputting an oscillation signal with a predetermined repetition frequency and controlling the repetition frequency according to the count value to output it as the output signal; and a controlling circuit for controlling the frequency regulating circuit to output the oscillation signal with the predetermined repetition frequency when the input of the reference signal breaks down.
摘要翻译： 数字相位同步电路包括相位比较电路，用于根据输出信号和外部输入参考信号之间的相位比较的结果来输出计数值; 频率调节电路，用于输入具有预定重复频率的振荡信号，并根据计数值控制重复频率，以输出其作为输出信号; 以及控制电路，用于当参考信号的输入分解时，控制频率调节电路输出具有预定重复频率的振荡信号。
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公开(公告)号：US5694068A
公开(公告)日：1997-12-02
申请号：US637608
申请日：1996-04-25
申请人： Yoshinori Rokugo
发明人： Yoshinori Rokugo
CPC分类号： H04J3/0632 , H03L7/087 , H03L7/0993 , H03L7/191
摘要： Using positive-phase or negative-phase clocks of phase count clock Pf.sub.0, a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been N-stage frequency divided and moreover, divided into M groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.
摘要翻译： 使用相位计数时钟Pf0的正相或负相位时钟，多级量化相位比较器M输出为多级量化的值，从第一和第N级分频器输出的输出信号的相位差，其中输入时钟和 数字PLL的输出时钟分别是N级分频，而且分为M组。 加法器将该相位差信息相加，并输出高级脉冲或延迟脉冲。 N1计数器响应高级脉冲计数，并输出增量脉冲，并在计数到2N1时经过设置为初始值N1。 响应于延迟脉冲，N1计数器倒计时，并且在向下计数到“0”时，都输出递减脉冲，并将其设置为初始值N1。
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公开(公告)号：US4935921A
公开(公告)日：1990-06-19
申请号：US99963
申请日：1987-09-23
摘要： In a cross-connection network, a plurality of asynchronous input digital signals can be cross-connected to a plurality of output lines by use of time switch. The input digital signals are pulse stuffed at a common higher bit rate and are synchronized to one another by attaching extra bits. The pulse stuffed signals are assigned into serial frames in a predetermined order by the multiplex technique and are interchanged from one to another by the time switch in the time division fashion. The frame-interchanged signal is demultiplexed to reproduce the pulse-stuffed signals which are sent out to the respective output lines assigned to the frames after removing extra bits. When the input digital signals are of higher order group, each of the higher order group digital signals is demultiplexed to lower order group signals which are pulse stuffed to be synchronized to the common higher bit rate. The pulse stuffed lower order signals are rearranged by the multiplex technique to reform each of the high order group signal which is synchronized to one another. The reformed higher order group signals are assigned in serial frames and are processed in the similar manner as described above. The frame-interchanged signals are reversely processed to be separated, demultiplexed, destuffed, and multiplexed to reproduce the input signals as the output signals.
摘要翻译： 在交叉连接网络中，多个异步输入数字信号可以通过使用时间切换与多个输出线交叉连接。 输入的数字信号以相同的较高比特率脉冲填充，并通过附加额外的比特来彼此同步。 脉冲填充信号通过多路复用技术以预定顺序被分配给串行帧，并且通过时分方式以时分交换方式从一个到另一个互换。 帧互换信号被解复用以再现脉冲填充信号，该脉冲填充信号在去除额外位之后发送到分配给帧的相应输出线。 当输入数字信号为高阶组时，高阶组数字信号中的每一个被解复用为脉冲填充的较低阶组信号以与公共较高比特率同步。 脉冲填充的低阶信号通过多路技术重新排列，以重新形成彼此同步的高阶组信号。 改进的高阶组信号以串行帧分配，并以与上述相似的方式进行处理。 帧互换的信号被反向处理以被分离，解复用，解消融和多路复用以再现作为输出信号的输入信号。
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公开(公告)号：US06496553B1
公开(公告)日：2002-12-17
申请号：US09215339
申请日：1998-12-18
申请人： Yoshinori Rokugo
发明人： Yoshinori Rokugo
IPC分类号： H03L708
CPC分类号： H04N5/04 , H03L7/08 , H03L7/181 , H04N5/126 , H04N5/4401 , H04N21/4305
摘要： A PLL is provided for reproducing a standard clock having a constant Jitter band from a random time information. This PLL is composed of a receiving counter 4-1 for counting the standard clock received from the transmitting side; a subtractor 4-3 for comparing between the count value of the receiving counter 4-1 which is read out each time when the receiving counter receives the count value from the transmitting counter; a differential time calculator for calculating a difference between the present count value and the preceding count value of the receiving counter; a first attenuator 4-5 for attenuating the output of the subtractor; a second attenuator 4-6 for further attenuating the output of the first attenuator; an integrator 4-7 for integrating the output of the second attenuator based on the differential time calculated by the differential time calculator; an adder 4-8 for adding the outputs of the adder and the integrator; a converter 4-9 for converting the result of the adder into a voltage signal; and a voltage control oscillator 4-10 for outputting a signal to the receiving counter based on the input of the voltage signal converted by the converter.
摘要翻译： 提供PLL，用于从随机时间信息再现具有恒定抖动频带的标准时钟。 该PLL由用于计数从发送侧接收的标准时钟的接收计数器4-1组成; 减法器4-3，用于在接收计数器从接收计数器接收到来自发送计数器的计数值时每次读出的接收计数器4-1的计数值进行比较; 用于计算当前计数值与接收计数器的先前计数值之间的差的差分时间计算器; 用于衰减减法器的输出的第一衰减器4-5; 第二衰减器4-6，用于进一步衰减第一衰减器的输出; 积分器4-7，用于基于由差分时间计算器计算的差分时间积分第二衰减器的输出; 加法器4-8，用于将加法器和积分器的输出相加; 转换器4-9，用于将加法器的结果转换成电压信号; 以及用于基于由转换器转换的电压信号的输入将信号输出到接收计数器的电压控制振荡器4-10。
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公开(公告)号：US5604774A
公开(公告)日：1997-02-18
申请号：US527353
申请日：1995-09-12
申请人： Yoshinori Rokugo , Masaaki Itoh
发明人： Yoshinori Rokugo , Masaaki Itoh
CPC分类号： H03L7/107 , H03L7/093 , H03L7/0993 , H04J3/076
摘要： Each of primary and secondary random-walk filters has longer and shorter time constants. A multi-valued phase comparator generates a start signal if a phase error generated when an abrupt frequency change occurs exceeds a given value. In response to the start signal, the primary and secondary random-walk filters are set to the shorter time constants. A timer is started by the start signal, and upon elapse of a predetermined period of time, sets the primary and secondary random-walk filters to the longer time constants.
摘要翻译： 每个主要和次要随机游走过滤器具有更长和更短的时间常数。 如果发生突然频率变化时产生的相位误差超过给定值，则多值相位比较器产生起始信号。 响应于起始信号，将主要和次要随机游走滤波器设置为较短的时间常数。 定时器由启动信号启动，经过预定时间后，将主次要随机游走滤波器设定为较长的时间常数。
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