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    COMPILING DEVICE AND COMPILING METHOD
    3.
    发明申请
    COMPILING DEVICE AND COMPILING METHOD 有权
    编译器和编译方法

    公开(公告)号：US20110138371A1

    公开(公告)日：2011-06-09

    申请号：US12876599

    申请日：2010-09-07

    申请人： Yasuki TANABE ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

    发明人： Yasuki TANABE ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

    IPC分类号： G06F9/45

    CPC分类号： G06F8/445

    摘要： According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

    摘要翻译： 根据一个实施例，编译用于使用帧存储器的源程序的编译装置包括：处理延迟量计算器，被配置为基于源程序的处理状态计算源程序中的多个处理任务之间的各个处理延迟量; 由进程任务处理的数据片段。 编译装置还包括行存储量计算器，其被配置为基于处理任务读取数据的帧存储器的访问范围来计算每个处理任务所需的各行行存储器大小，以及指令代码转换器，被配置为转换 基于处理延迟量和行存储器大小，可以在流水线中执行的指令代码的多个处理任务。

    Image processing apparatus and image processing system
    4.
    发明授权
    Image processing apparatus and image processing system 有权
    图像处理装置和图像处理系统

    公开(公告)号：US08345113B2

    公开(公告)日：2013-01-01

    申请号：US12512593

    申请日：2009-07-30

    申请人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

    发明人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

    IPC分类号： H04N5/228

    CPC分类号： H04N5/77 ,  G06F9/30043 ,  G06F9/35 ,  G06F9/355

    摘要： An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

    摘要翻译： 图像处理装置具有：数据存储器，被配置为存储图像数据; RP寄存器，被配置为保存指示图像数据的帧中的RP的位置的二维地址; 以及RP控制部，被配置为基于帧的宽度和高度来控制由RP寄存器保持的二维地址。 此外，图像处理装置具有地址计算单元，其被配置为当基于具有用于通过组合从RP指定二维相对位置的字段的指令代码从数据存储器读取目标像素数据时， 基于二维地址，立即值的组合和帧的宽度，计算存储读取目标像素数据的地址。

    Image coding-decoding apparatus with efficient memory access
    6.
    发明授权
    Image coding-decoding apparatus with efficient memory access 失效
    具有高效存储器访问的图像编码解码装置

    公开(公告)号：US5541658A

    公开(公告)日：1996-07-30

    申请号：US265929

    申请日：1994-06-27

    申请人： Shunichi Ishiwata

    发明人： Shunichi Ishiwata

    IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N9/64 ,  H04N11/04 ,  H04N7/12

    CPC分类号： H04N11/042 ,  H04N19/423 ,  H04N19/61 ,  H04N9/64

    摘要： An image coding and decoding apparatus which can produce an improved amount of the effective data per time unit especially in a case where the image data are processed in the field unit. The apparatus includes: a subtracting unit which subtracts a reference image signal from an input image signal; a intra-frame coding unit which codes the image signal sent from the subtracting unit, and data on a reference image signal; and an inter-frame prediction unit which performs an image prediction process among previous or future image data and which sends the reference image signal to the subtracting unit and the intra-frame coding unit, wherein the apparatus is characterized in that the inter-frame prediction unit includes an input-output circuit in which pixel data of luminance signals are separated from those of color signals, and the thus separated pixel data are arranged in a single row of a horizontal direction as a minimum unit, so that the amount of effective data accessible in a time unit can be significantly increased in the course of processing data in the field unit.

    摘要翻译： 特别是在图像数据在现场单元中进行处理的情况下，可以每时间单位产生改善量的有效数据的图像编码和解码装置。 该装置包括：减法单元，其从输入图像信号中减去参考图像信号; 编码从减法单元发送的图像信号的帧内编码单元和参考图像信号的数据; 以及帧间预测单元，其执行先前或未来图像数据中的图像预测处理，并将参考图像信号发送到减法单元和帧内编码单元，其中该装置的特征在于帧间预测 单元包括输入输出电路，其中亮度信号的像素数据与彩色信号的像素数据分离，并且将这样分离的像素数据以单行水平方向布置为最小单位，使得有效数据量 在现场单位处理数据的过程中，可以在时间单位中进行访问。

    COMPILING APPARATUS, COMPILING METHOD, AND PROGRAM PRODUCT
    7.
    发明申请
    COMPILING APPARATUS, COMPILING METHOD, AND PROGRAM PRODUCT 审中-公开
    编译设备，编译方法和程序产品

    公开(公告)号：US20100229162A1

    公开(公告)日：2010-09-09

    申请号：US12559962

    申请日：2009-09-15

    申请人： Ryuji HADA ,  Takashi Miyamori ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Takahisa Wada ,  Yasuki Tanabe ,  Katsuyuki Kimura ,  Shunichi Ishiwata

    发明人： Ryuji HADA ,  Takashi Miyamori ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Takahisa Wada ,  Yasuki Tanabe ,  Katsuyuki Kimura ,  Shunichi Ishiwata

    IPC分类号： G06F9/45 ,  G06F9/30

    CPC分类号： G06F8/45 ,  G06F9/4494

    摘要： A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.

    摘要翻译： 编译装置包括指令序列层次图生成单元，其通过排列单位图来生成指示序列层次图，对于每一个，通过由一个指令序列中包含的多个微指令实现的数据路径被分配， 包括在目标处理器中的各个功能单元是节点，并且功能单元之间的数据线是边缘，以对应于多个指令序列的执行顺序，并且通过连接具有与硬件对应的边缘的排列的单位图 路径能够跨越指令序列建立数据路径; 数据路径分配单元，其向构成指令序列层次图的每个单位图分配数据路径; 以及对象程序输出单元，其基于分配给指令序列层次图的数据路径生成指令序列组。

    IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING SYSTEM
    8.
    发明申请
    IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING SYSTEM 有权
    图像处理设备和图像处理系统

    公开(公告)号：US20100103282A1

    公开(公告)日：2010-04-29

    申请号：US12512593

    申请日：2009-07-30

    申请人： Keiri NAKANISHI ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

    发明人： Keiri NAKANISHI ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

    IPC分类号： H04N5/76

    CPC分类号： H04N5/77 ,  G06F9/30043 ,  G06F9/35 ,  G06F9/355

    摘要： An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

    摘要翻译： 图像处理装置具有：数据存储器，被配置为存储图像数据; RP寄存器，被配置为保存指示图像数据的帧中的RP的位置的二维地址; 以及RP控制部，被配置为基于帧的宽度和高度来控制由RP寄存器保持的二维地址。 此外，图像处理装置具有地址计算单元，其被配置为当基于具有用于通过组合从RP指定二维相对位置的字段的指令代码从数据存储器读取目标像素数据时， 基于二维地址，立即值的组合和帧的宽度，计算存储读取目标像素数据的地址。

    Dicing/die bonding sheet
    10.
    发明申请
    Dicing/die bonding sheet 有权
    切片/切片粘合片

    公开(公告)号：US20070026572A1

    公开(公告)日：2007-02-01

    申请号：US10556535

    申请日：2005-03-15

    申请人： Keiichi Hatakeyama ,  Michio Uruno ,  Takayuki Matsuzaki ,  Yasumasa Morishima ,  Kenji Kita ,  Shunichi Ishiwata

    发明人： Keiichi Hatakeyama ,  Michio Uruno ,  Takayuki Matsuzaki ,  Yasumasa Morishima ,  Kenji Kita ,  Shunichi Ishiwata

    IPC分类号： H01L21/00

    CPC分类号： C09J163/10 ,  C08L63/00 ,  C08L2666/02 ,  C08L2666/22 ,  C09J7/35 ,  C09J133/068 ,  C09J161/06 ,  C09J161/28 ,  C09J175/14 ,  C09J2201/36 ,  C09J2201/606 ,  C09J2203/326 ,  C09J2461/00 ,  C09J2463/00 ,  C09J2475/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/73265 ,  H01L2224/83191

    摘要： The present invention provides a dicing/die bonding sheet which can be used as a dicing tape during dicing, enables ready separation of the semiconductor element and the adhesive layer from the pressure-sensitive adhesive layer during pickup, and in which the adhesive layer has satisfactory adhesiveness as a die bonding material. A dicing/die bonding sheet in which the pressure-sensitive adhesive layer comprises a compound (A), containing intramolecular, radiation curable carbon-carbon double bonds with an iodine value of 0.5 to 20, and at least one compound (B) selected from a group consisting of polyisocyanates, melamine-formaldehyde resins, and epoxy resins, and the adhesive layer comprises an epoxy resin (a), a phenolic resin (b) with a hydroxyl equivalent of at least 150 g/eq., an epoxy group-containing acrylic copolymer (c), comprising from 0.5 to 6% by weight of glycidyl acrylate or glycidyl methacrylate, and with a weight average molecular weight of at least 100,000, a filler (d), and a curing accelerator (e).

    摘要翻译： 本发明提供一种切割/切片接合片，其可以在切割时用作切割带，能够在拾取期间将半导体元件和粘合剂层与压敏粘合剂层容易地分离，并且其中粘合剂层具有令人满意的 作为芯片接合材料的粘合性。 一种切片/芯片粘接片，其中所述压敏粘合剂层包含含有碘值为0.5至20的分子内，可辐射固化碳 - 碳双键的化合物（A）和至少一种选自以下的化合物（B）： 由聚异氰酸酯，三聚氰胺 - 甲醛树脂和环氧树脂组成的组，并且粘合剂层包含环氧树脂（a），羟基当量至少为150g / eq的酚醛树脂（b），环氧基 - 含有丙烯酸共聚物（c），包含0.5-6重量％的丙烯酸缩水甘油酯或甲基丙烯酸缩水甘油酯，重均分子量至少为100,000，填料（d）和固化促进剂（e）。