公开(公告)号：US20050200413A1

公开(公告)日：2005-09-15

申请号：US11077392

申请日：2005-03-10

Applicant: Keitaro Fujimori ,  Mihiro Nonoyama ,  Yukinari Shibata ,  Yoshiteru Ono ,  Hiroyasu Honda ,  Yoshiro Iwasa

Inventor： Keitaro Fujimori ,  Mihiro Nonoyama ,  Yukinari Shibata ,  Yoshiteru Ono ,  Hiroyasu Honda ,  Yoshiro Iwasa

IPC: H05K1/02 ,  G06F3/14 ,  G09G5/00 ,  H01L23/538 ,  H01L23/66 ,  H01L25/18 ,  H03F3/45 ,  H05K1/00 ,  H05K1/14 ,  H05K1/18

CPC classification number: H01L25/18 ,  G06F3/14 ,  G06F3/1423 ,  G09G5/006 ,  H01L23/5387 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/148 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09727 ,  Y10S370/912 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flexible substrate including: a first part provided with a first device DV1; a second part provided with a second device; a wiring part placed between the first part and the second part and including a plurality of wirings for coupling the first device and the second device; the first device including at least a first data transfer control unit, the second device including at least a second data transfer control unit, the first data transfer control unit and the second data transfer control unit transferring data by using a differential signal, and the plurality of wirings for coupling the first device and the second device including at least one differential signal line pair for transferring data by using a differential signal.

Abstract translation: 一种柔性基板，包括：具有第一装置DV1的第一部分; 第二部分，设置有第二装置; 布置在所述第一部分和所述第二部分之间并且包括用于联接所述第一装置和所述第二装置的多个布线; 所述第一装置至少包括第一数据传送控制单元，所述第二装置至少包括第二数据传送控制单元，所述第一数据传送控制单元和所述第二数据传送控制单元通过使用差分信号传送数据，并且所述多个 用于耦合第一器件和第二器件的布线，包括用于通过使用差分信号传送数据的至少一个差分信号线对。

公开(公告)号：US07456701B2

公开(公告)日：2008-11-25

申请号：US11077392

申请日：2005-03-10

Applicant: Keitaro Fujimori ,  Mihiro Nonoyama ,  Yukinari Shibata ,  Yoshiteru Ono ,  Hiroyasu Honda ,  Yoshiro Iwasa

Inventor： Keitaro Fujimori ,  Mihiro Nonoyama ,  Yukinari Shibata ,  Yoshiteru Ono ,  Hiroyasu Honda ,  Yoshiro Iwasa

IPC: G06F13/00 ,  H03H7/38

CPC classification number: H01L25/18 ,  G06F3/14 ,  G06F3/1423 ,  G09G5/006 ,  H01L23/5387 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/148 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09727 ,  Y10S370/912 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flexible substrate including: a first part provided with a first device DV1; a second part provided with a second device; a wiring part placed between the first part and the second part and including a plurality of wirings for coupling the first device and the second device; the first device including at least a first data transfer control unit, the second device including at least a second data transfer control unit, the first data transfer control unit and the second data transfer control unit transferring data by using a differential signal, and the plurality of wirings for coupling the first device and the second device including at least one differential signal line pair for transferring data by using a differential signal.

Abstract translation: 一种柔性基板，包括：具有第一装置DV1的第一部分; 第二部分，设置有第二装置; 布置在所述第一部分和所述第二部分之间并且包括用于联接所述第一装置和所述第二装置的多个布线; 所述第一装置至少包括第一数据传送控制单元，所述第二装置至少包括第二数据传送控制单元，所述第一数据传送控制单元和所述第二数据传送控制单元通过使用差分信号传送数据，并且所述多个 用于耦合第一器件和第二器件的布线，包括用于通过使用差分信号传送数据的至少一个差分信号线对。

公开(公告)号：US06721933B2

公开(公告)日：2004-04-13

申请号：US09984219

申请日：2001-10-29

Applicant: Yoshiro Iwasa

Inventor： Yoshiro Iwasa

IPC: G06F1750

CPC classification number: G06F17/5072 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and an input/output (I/O) cell placement method can cope with reduction of the chip area and increase in the number of pins, without changing a core transistor region inside the semiconductor device. A semiconductor chip of the semiconductor device has a core transistor region, an I/O cell placement region and a pad placement region. At least two columns of I/O cells to be placed in the I/O cell placement region of the semiconductor chip are arranged in a direction perpendicular to the arranging direction of pads arranged along the outer peripheral portion of the semiconductor chip and in such a manner that the longitudinal direction (height directions) of the chip is parallel to the pad arranging direction.

Abstract translation: 半导体器件和输入/输出（I / O）单元布置方法可以在不改变半导体器件内部的核心晶体管区域的情况下应对芯片面积的减小和引脚数量的增加。 半导体器件的半导体芯片具有核心晶体管区域，I / O单元放置区域和焊盘放置区域。 要放置在半导体芯片的I / O单元放置区域中的I / O单元的至少两列布置在与沿着半导体芯片的外周部分布置的焊盘排列方向垂直的方向上， 使得芯片的纵向（高度方向）平行于焊盘排列方向的方式。

公开(公告)号：US06713755B1

公开(公告)日：2004-03-30

申请号：US09654550

申请日：2000-09-01

Applicant: Yoshiro Iwasa

Inventor： Yoshiro Iwasa

IPC: G01J508

CPC classification number: G01J1/04 ,  G01J1/0204 ,  G01J1/0425 ,  G02B6/42 ,  G02B6/421 ,  G02B6/424 ,  G02B6/4253 ,  G02B6/428 ,  G02B6/43 ,  H01L2224/49171

Abstract: A semiconductor device that is capable of correctly transferring signals at high speed. The semiconductor device includes a semiconductor chip, a light-receiving element formed in the semiconductor chip for receiving an optical signal, and a glass fiber as an optical signal transfer device connected to the light-receiving element for transferring the optical signal into the semiconductor chip. Optical signals have a smaller attenuation of signal amplitude and have a higher transfer speed compared to electrical signals. Therefore, by transferring signals in the form of optical signals, the semiconductor device that can correctly transfer signals at high speed is obtained.

Abstract translation: 能够高速正确地传送信号的半导体装置。 半导体器件包括半导体芯片，形成在用于接收光信号的半导体芯片中的光接收元件，以及玻璃光纤作为连接到光接收元件的光信号传输器件，用于将光信号传输到半导体芯片中 。 光信号的信号幅度衰减较小，与电信号相比具有较高的传输速度。 因此，通过以光信号的形式传送信号，可以获得能够高速正确传送信号的半导体装置。

公开(公告)号：US08866829B2

公开(公告)日：2014-10-21

申请号：US12845983

申请日：2010-07-29

Applicant: Hideki Ogawa ,  Yoshiro Iwasa

Inventor： Hideki Ogawa ,  Yoshiro Iwasa

IPC: G06T1/60 ,  G11C5/02 ,  H01L23/00 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395

CPC classification number: G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G2360/18 ,  G11C5/02 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An integrated circuit device includes: a first pad to an ith pad connected to a first memory pad to an ith memory pad of a memory stacked in the integrated circuit device; a jth pad to a kth pad connected to a jth memory pad to a kth (1

Abstract translation: 集成电路装置包括：第一焊盘，连接到第一存储器焊盘的第i焊盘到集成电路器件中堆叠的存储器的第i个存储器焊盘; 连接到第j个存储器焊盘的第k个焊盘到第k个焊盘到存储器的第k个（1