公开(公告)号：US20060199330A1

公开(公告)日：2006-09-07

申请号：US11363996

申请日：2006-03-01

申请人： Yoshitaka Nakamura ,  Yoshihiro Takaishi

发明人： Yoshitaka Nakamura ,  Yoshihiro Takaishi

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10894 ,  H01L27/10897

摘要： A method of manufacturing a semiconductor memory according to the present invention includes steps of forming an insulating film, into which a conductive plug connected to a source or a drain in a transistor in a memory cell region and into which a first conductive layer which will become a part of a circuit in a peripheral circuit region are buried, on a semiconductor substrate, forming a first interlayer insulating film on the insulating film, forming, in the first interlayer insulating film, conductive plugs for connecting a first conductive layer and a second conductive layer arranged in a layer upper than the first interlayer insulating film, forming lower electrode of the capacitor in the first interlayer insulating film after the connection plugs are formed, forming capacitance insulating film, and forming upper electrode of the capacitor.

摘要翻译： 根据本发明的制造半导体存储器的方法包括以下步骤：形成绝缘膜，在绝缘膜中连接到存储单元区域中的晶体管中的源极或漏极的导电插塞并且将成为第一导电层 外围电路区域中的电路的一部分被埋在半导体衬底上，在绝缘膜上形成第一层间绝缘膜，在第一层间绝缘膜中形成用于连接第一导电层和第二导电层的导电插塞 在上述第一层间绝缘膜的上方布置层，在形成连接插塞之后，在第一层间绝缘膜中形成电容器的下部电极，形成电容绝缘膜，形成电容器的上部电极。

公开(公告)号：US08378417B2

公开(公告)日：2013-02-19

申请号：US12662127

申请日：2010-03-31

申请人： Kazuo Ogawa ,  Yoshihiro Takaishi

发明人： Kazuo Ogawa ,  Yoshihiro Takaishi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/423 ,  H01L29/74 ,  H01L31/111 ,  H01L27/148 ,  H01L29/768

CPC分类号： H01L29/7827 ,  H01L29/1087 ,  H01L29/66666

摘要： A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.

摘要翻译： 半导体器件包括半导体衬底; 半导体衬底中的第一导电类型的阱; 第一个元素; 和第一垂直晶体管。 第一个元素为井提供潜力，第一个元素在井中。 第一元件可以包括但不限于第一导电类型的第一柱体。 第一柱体具有包括第一导电类型的第一扩散层的上部。 第一扩散层的杂质浓度大于阱。 第一垂直晶体管在井中。 第一垂直晶体管可以包括第一导电类型的第二柱体。 第二柱体具有包括第二导电类型的第二扩散层的上部。

公开(公告)号：US20120100682A1

公开(公告)日：2012-04-26

申请号：US13253100

申请日：2011-10-05

申请人： Yuki Munetaka ,  Yoshihiro Takaishi

发明人： Yuki Munetaka ,  Yoshihiro Takaishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/66666

摘要： A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection.

摘要翻译： 半导体器件的制造方法包括以下步骤：在硅衬底的主表面上形成绝缘柱; 在绝缘柱的侧面上形成保护膜; 在硅衬底的主表面上形成硅柱; 在所述硅柱的侧面上形成栅极绝缘膜; 以及形成第一和第二栅电极以彼此接触并分别覆盖硅柱和绝缘柱的侧表面。 根据本制造方法，在绝缘柱的侧面上形成保护膜作为虚拟柱，从而防止了当通道的硅柱被加工成晶体管时，伪柱被腐蚀。 因此，可以降低栅电极断开的发生概率。

公开(公告)号：US07910986B2

公开(公告)日：2011-03-22

申请号：US12130542

申请日：2008-05-30

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L29/78

CPC分类号： H01L27/0207 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/24

摘要： A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers (11, 12) provided in a lower part and an upper part, respectively of the silicon pillar, a bit line connected to the diffusion layer (11), and a memory element connected to the diffusion layer (12). The bit line includes a silicon material region in contact with the diffusion layer (11), and a low-resistance region including a material having lower electric resistance than that of the silicon material region. As a result, the resistance of the bit line embedded in the substrate can be decreased.

摘要翻译： 半导体存储器件包括硅柱，经由栅极绝缘膜覆盖硅柱的侧表面的栅电极，分别设置在硅柱的下部和上部的扩散层（11,12）， 连接到扩散层（11）的位线以及连接到扩散层（12）的存储元件。 位线包括与扩散层（11）接触的硅材料区域，以及包括具有比硅材料区域低的电阻的材料的低电阻区域。 结果，可以降低嵌入在基板中的位线的电阻。

公开(公告)号：US07528454B2

公开(公告)日：2009-05-05

申请号：US11526014

申请日：2006-09-25

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L21/8242

CPC分类号： H01L27/0207 ,  H01L27/10897

摘要： The present invention provides a semiconductor memory which has sense amplifiers, each including a pair of MOSFETs having complete symmetry in regard to not only the shape but also to the impurity profile in a diffusion layer, and the present invention is also capable of reducing variations in electric characteristics, and provides a method of manufacturing the same. Annular gate electrodes 12a, 12b are formed on diffusion layer 11. Gate electrodes 13 are formed simultaneously with a sense amplifier along edges of diffusion layer 11 to bestride the boundary between diffusion layer 11 and r shallow trench isolation area 20. Contacts 16 are formed on diffusion layer 11; contacts 17a, 17b on diffusion layer 11 within annular gate electrodes 12a, 12b, respectively; and contacts 18 on gate electrodes 12a, 12b of the sense amplifier. All components are arranged in symmetry, and gate electrodes 13 running along the edges of diffusion layer 11 hold the same spacings 14, 15 between gate electrodes 12a, 12b and gate electrodes 13, so that an impurity profile in diffusion layer 11 is not affected by the edges of shallow trench isolation area 20. Consequently, the MOSFETs are arranged in complete symmetry and contribute to a reduction of variation in the characteristics.

摘要翻译： 本发明提供了一种具有读出放大器的半导体存储器，每一个都包括一对对于扩散层中不仅形状而且与杂质分布完全对称的MOSFET，本发明还能够减小 电特性，并提供其制造方法。 环形栅电极12a，12b形成在扩散层11上。栅电极13与扩散层11的边缘的读出放大器同时形成，以最佳化扩散层11和浅沟槽隔离区域20之间的边界。触点16形成在 扩散层11; 分别在环形栅电极12a，12b内的扩散层11上的接触17a，17b; 以及在读出放大器的栅电极12a，12b上的触点18。 所有的部件都是对称的，并且沿扩散层11的边缘延伸的栅电极13在栅电极12a，12b和栅电极13之间保持相同的间隔14,15，使得扩散层11中的杂质分布不受 浅沟槽隔离区域20的边缘。因此，MOSFET被完全对称地布置并且有助于降低特性的变化。

公开(公告)号：US20090085088A1

公开(公告)日：2009-04-02

申请号：US12238593

申请日：2008-09-26

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L29/00

CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L27/10894 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66666

摘要： A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low voltage transistor. Each of the unit transistors may include a vertically extending portion of semiconductor providing a channel region and having a uniform height, a gate insulating film extending along a side surface of the vertically extending portion of semiconductor, a gate electrode separated by the gate insulating film from the vertically extending portion of semiconductor, and upper and lower diffusion regions being respectively disposed near the top and bottom of the vertically extending portion of semiconductor. The greater number of the unit transistors are connected in series to each other and have gate electrodes eclectically connected to each other.

摘要翻译： 半导体器件包括衬底上的低电压和高压晶体管。 低压晶体管由至少一个单位晶体管构成。 高压晶体管由比配置低压晶体管的至少一个单位晶体管更多数量的单位晶体管构成。 每个单位晶体管可以包括提供沟道区并具有均匀高度的半导体的垂直延伸部分，沿着半导体的垂直延伸部分的侧表面延伸的栅极绝缘膜，由栅极绝缘膜分离的栅电极 半导体的垂直延伸部分，以及上部和下部扩散区域分别设置在半导体的垂直延伸部分的顶部和底部附近。 较大数量的单位晶体管彼此串联连接并且具有互相连接的栅电极。

公开(公告)号：US20080227253A1

公开(公告)日：2008-09-18

申请号：US12049414

申请日：2008-03-17

申请人： Kazuo Ogawa ,  Yoshihiro Takaishi

发明人： Kazuo Ogawa ,  Yoshihiro Takaishi

IPC分类号： H01L21/8242

CPC分类号： H01L27/10808 ,  H01L27/10888

摘要： A method of manufacturing a semiconductor device which includes a first gate wiring layer and a second gate wiring layer adjacent to each other; a first diffused layer provided on a side between the wiring layers; a second diffused layer provided on one side external to the side between the wiring layers; and a third diffused layer provided on the other side external to the side between the wiring layers, the method including: forming a first mask including an opening; implanting a channel impurity for threshold voltage control using the first mask; forming a first diffused layer using the first mask by implanting a first impurity; forming a first gate wiring layer and a second gate wiring layer after removing the first mask; and forming a second diffused layer and a third diffused layer using the first gate wiring layer and the second gate wiring layer as a second mask by implanting a second impurity.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括彼此相邻的第一栅极布线层和第二栅极布线层; 设置在所述布线层之间的一侧上的第一扩散层; 设置在所述布线层之间的一侧外侧的一侧的第二扩散层; 以及设置在所述布线层之间的一侧的另一侧的第三扩散层，所述方法包括：形成包括开口的第一掩模; 使用第一掩模注入用于阈值电压控制的沟道杂质; 通过注入第一杂质，使用第一掩模形成第一扩散层; 在去除第一掩模之后形成第一栅极布线层和第二栅极布线层; 以及通过注入第二杂质，使用第一栅极布线层和第二栅极布线层形成第二扩散层和第三扩散层作为第二掩模。

公开(公告)号：US06914336B2

公开(公告)日：2005-07-05

申请号：US09764880

申请日：2001-01-23

申请人： Takeo Matsuki ,  Yoshihiro Takaishi

发明人： Takeo Matsuki ,  Yoshihiro Takaishi

IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52

CPC分类号： H01L21/32053 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a structure for a semiconductor device, capable of eliminating the generation of defective products due to poor connection. In the present semiconductor device, an n-type high concentration diffusion layer 2 is selectively formed on the P-type silicon substrate 1, and on the diffusion layer 2, a silicon oxide film 3 is formed as a first interlayer insulating film 3. A silicon plug 4 is disposed on the n-type high concentration diffusion layer 2. On the top end surface of the polysilicon plug 4, a silicide pad 5 is formed in a self-aligning manner such that the width of the silicide pad 5 is larger than that of the polysilicon plug 4. A second interlayer insulating film is formed so as to cover the first interlayer insulating film 3 and the silicide pad 5, and a tungsten plug 7 is disposed on the silicide pad 5. On the second interlayer insulating film, wiring 8, made of an aluminum-copper alloy and connected to the tungsten plug, is formed.

摘要翻译： 本发明提供一种半导体器件的结构，其能够消除由于连接不良导致的不良品的产生。 在本半导体装置中，在P型硅基板1上选择性地形成n型高浓度扩散层2，在扩散层2上形成作为第一层间绝缘膜3的氧化硅膜3。 硅插头4设置在n型高浓度扩散层2上。在多晶硅插塞4的顶端表面上，以自对准方式形成硅化物焊盘5，使得硅化物焊盘5的宽度较大 形成第二层间绝缘膜以覆盖第一层间绝缘膜3和硅化物垫5，并且在硅化物垫5上设置钨插塞7.在第二层间绝缘膜上 形成由铝 - 铜合金制成并连接到钨插头的布线8。

公开(公告)号：US5798544A

公开(公告)日：1998-08-25

申请号：US242345

申请日：1994-05-13

申请人： Shuichi Ohya ,  Masato Sakao ,  Yoshihiro Takaishi ,  Kiyonori Kajiyana ,  Takeshi Akimoto ,  Shizuo Oguro ,  Seiichi Shishiguchi

发明人： Shuichi Ohya ,  Masato Sakao ,  Yoshihiro Takaishi ,  Kiyonori Kajiyana ,  Takeshi Akimoto ,  Shizuo Oguro ,  Seiichi Shishiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10823 ,  H01L27/10808

摘要： Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capacitor having a capacitor electrode connected to the source region through a contact hole provided in the first and second insulating film.

摘要翻译： 这里公开了一种半导体存储器件，其包括多个存储单元，每个存储单元包括有源区，该有源区通过在半导体衬底中形成的一对沟槽隔离区而在列方向上限定，并且在行方向上由隔离栅导体线形成 覆盖基板的第一栅极绝缘膜，选择性地形成在有源区中的源极和漏极区域，以限定单元晶体管的沟道区，形成在沟道区上的第二栅极绝缘膜，形成在第二栅极上的字线 绝缘膜，覆盖有源区和字线的第一绝缘膜，形成在第一绝缘膜上以与隔离栅导体重叠的位线;形成在第一绝缘膜中的位线连接导体，以将漏区连接到 位线与位线的侧壁表面接触，覆盖位线的第二绝缘膜和第一绝缘f 以及具有通过设置在第一和第二绝缘膜中的接触孔连接到源极区的电容器电极的存储电容器。

公开(公告)号：US5726083A

公开(公告)日：1998-03-10

申请号：US562224

申请日：1995-11-28

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L21/265 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8238

CPC分类号： H01L27/10844 ,  H01L27/10852 ,  H01L28/40

摘要： When tantalum oxide is used for a dielectric film of a stacked type storage capacitor forming a memory cell together with a switching transistor, heat treatments are limited to 530 degrees centigrade in the stages after the deposition of the tantalum oxide, and leakage current across the tantalum oxide is drastically decreased.

摘要翻译： 当将钽氧化物用于与开关晶体管一起形成存储单元的层叠型存储电容器的电介质膜时，在氧化钽沉积之后的阶段将热处理限制在530摄氏度，并且跨钽的漏电流 氧化物急剧下降。