公开(公告)号：US5798544A

公开(公告)日：1998-08-25

申请号：US242345

申请日：1994-05-13

申请人： Shuichi Ohya ,  Masato Sakao ,  Yoshihiro Takaishi ,  Kiyonori Kajiyana ,  Takeshi Akimoto ,  Shizuo Oguro ,  Seiichi Shishiguchi

发明人： Shuichi Ohya ,  Masato Sakao ,  Yoshihiro Takaishi ,  Kiyonori Kajiyana ,  Takeshi Akimoto ,  Shizuo Oguro ,  Seiichi Shishiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10823 ,  H01L27/10808

摘要： Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capacitor having a capacitor electrode connected to the source region through a contact hole provided in the first and second insulating film.

摘要翻译： 这里公开了一种半导体存储器件，其包括多个存储单元，每个存储单元包括有源区，该有源区通过在半导体衬底中形成的一对沟槽隔离区而在列方向上限定，并且在行方向上由隔离栅导体线形成 覆盖基板的第一栅极绝缘膜，选择性地形成在有源区中的源极和漏极区域，以限定单元晶体管的沟道区，形成在沟道区上的第二栅极绝缘膜，形成在第二栅极上的字线 绝缘膜，覆盖有源区和字线的第一绝缘膜，形成在第一绝缘膜上以与隔离栅导体重叠的位线;形成在第一绝缘膜中的位线连接导体，以将漏区连接到 位线与位线的侧壁表面接触，覆盖位线的第二绝缘膜和第一绝缘f 以及具有通过设置在第一和第二绝缘膜中的接触孔连接到源极区的电容器电极的存储电容器。

公开(公告)号：US5548157A

公开(公告)日：1996-08-20

申请号：US441573

申请日：1995-05-15

申请人： Masato Sakao ,  Shuichi Ohya

发明人： Masato Sakao ,  Shuichi Ohya

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L28/40

摘要： In a semiconductor device having a first insulator layer on a semiconductor substrate and accumulation electrode layers overlying the first insulator layer, second insulator layers overlie predetermined areas of the first insulator layer and side electrode surfaces of the accumulation electrode layers. Each of the second insulator layers has a primary dielectric constant. A dielectric layer overlies upper surfaces of the accumulation electrode layers and the second insulator layers and has a secondary dielectric constant which is higher than the primary dielectric constant. An opposed electrode layer overlies the dielectric layer.

公开(公告)号：US5466964A

公开(公告)日：1995-11-14

申请号：US116569

申请日：1993-09-07

申请人： Masato Sakao ,  Shuichi Ohya

发明人： Masato Sakao ,  Shuichi Ohya

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/02 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L28/40

摘要： In a semiconductor device having a first insulator layer on a semiconductor substrate and accumulation electrode layers overlying the first insulator layer, second insulator layers overlie predetermined areas of the first insulator layer and side electrode surfaces of the accumulation electrode layers. Each of the second insulator layers has a primary dielectric constant. A dielectric layer overlies upper surfaces of the accumulation electrode layers and the second insulator layers and has a secondary dielectric constant which is higher than the primary dielectric constant. An opposed electrode layer overlies the dielectric layer.

摘要翻译： 在半导体衬底上具有第一绝缘体层和覆盖在第一绝缘体层上的堆积电极层的半导体器件中，第二绝缘体层覆盖在第一绝缘体层的预定区域和积聚电极层的侧面电极表面上。 每个第二绝缘体层具有初级介电常数。 电介质层覆盖在积聚电极层和第二绝缘体层的上表面上，并且具有高于初级介电常数的二次介电常数。 相对的电极层覆盖在电介质层上。

公开(公告)号：US5698467A

公开(公告)日：1997-12-16

申请号：US742811

申请日：1996-11-01

申请人： Masato Sakao ,  Yoshihiro Takaishi

发明人： Masato Sakao ,  Yoshihiro Takaishi

IPC分类号： H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/31053

摘要： In a method of manufacturing an insulation layer on a semiconductor substrate, a first insulation film is deposited on the semiconductor substrate more thicker than a wiring layer formed on the semiconductor substrate. The first insulation film is mechano-chemically polished to expose a void formed in the first insulation film. The first insulation film is etched to widen an entrance portion of the void. A second insulation film is formed on the first insulation film to be embedded into the void. The second insulation film is etched at least to the first insulation film, with a part of the second insulation film left within the void. The exposed first insulation film and the left second insulation film has a flat surface.

摘要翻译： 在半导体衬底上制造绝缘层的方法中，在比半导体衬底上形成的布线层更厚的半导体衬底上沉积第一绝缘膜。 第一绝缘膜被机械化学抛光以暴露形成在第一绝缘膜中的空隙。 第一绝缘膜被蚀刻以加宽空隙的入口部分。 在第一绝缘膜上形成第二绝缘膜以嵌入空隙中。 第二绝缘膜至少蚀刻到第一绝缘膜上，第二绝缘膜的一部分留在空隙内。 露出的第一绝缘膜和左第二绝缘膜具有平坦的表面。

公开(公告)号：US5759889A

公开(公告)日：1998-06-02

申请号：US781960

申请日：1996-12-20

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L21/285 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/105

摘要： In a method for manufacturing a semiconductor device incorporating a DRAM section and a logic circuit section, a refractory metal layer is formed to cover a bit line of the DRAM section, and a gate electrode and impurity diffusion regions of the logic circuit section. Then, a heating operation is performed upon sadi refractory metal layer, so that metal silicide layers are formed in the bit line of the DRAM section, and the gate electrode and the impurity diffusion regions of the logic circuit section.

摘要翻译： 在制造具有DRAM部分和逻辑电路部分的半导体器件的制造方法中，形成难熔金属层以覆盖DRAM部分的位线，以及逻辑电路部分的栅极电极和杂质扩散区域。 然后，在sadi难熔金属层上进行加热操作，使得在DRAM部分的位线以及逻辑电路部分的栅电极和杂质扩散区域中形成金属硅化物层。

公开(公告)号：US5652446A

公开(公告)日：1997-07-29

申请号：US530994

申请日：1995-09-20

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/55 ,  H01L27/10808 ,  H01L28/40

摘要： There is provided a semiconductor device, including: a semiconductor substrate having a major surface; a first insulating film formed on the major surface of the semiconductor substrate; a plurality of first conductive members spaced apart from each other on the first insulating film and formed to be connected to the semiconductor substrate; a plurality of storage electrodes formed on the first insulating film at positions respectively corresponding to the first conductive members; a plurality of high-permittivity films respectively stacked on the plurality of storage electrodes; a plurality of first counter electrodes respectively stacked on the plurality of high-permittivity films; a second insulating film, having a permittivity much lower than a permittivity of each of the high-permittivity films, for insulating the first conductive members, the high-permittivity films, and the first counter electrodes, respectively; and a second counter electrode, formed on the second insulating film, for connecting adjacent first counter electrodes on an upper surface of the second counter electrode, and a method of manufacturing the semiconductor device.

摘要翻译： 提供了一种半导体器件，包括：具有主表面的半导体衬底; 形成在所述半导体衬底的主表面上的第一绝缘膜; 多个第一导电构件，其在所述第一绝缘膜上彼此间隔开并形成为连接到所述半导体衬底; 多个存储电极，形成在分别对应于第一导电部件的位置处的第一绝缘膜上; 分别堆叠在所述多个存储电极上的多个高电容率膜; 分别堆叠在所述多个高介电常数膜上的多个第一对置电极; 第二绝缘膜，具有比每个高电容率膜的介电常数低得多的介电常数，分别用于绝缘第一导电构件，高电容率膜和第一对置电极; 以及第二对置电极，形成在所述第二绝缘膜上，用于连接所述第二对置电极的上表面上的相邻的第一对置电极，以及制造所述半导体器件的方法。

公开(公告)号：US06696720B2

公开(公告)日：2004-02-24

申请号：US10131045

申请日：2002-04-25

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L27/0288 ,  H01L27/10852 ,  H01L28/40

摘要： A semiconductor device of the present invention comprises a capacitor portion composed of a lower electrode, a capacitor insulator film, and an upper electrode sequentially stacked on an inter-layer insulator film on a semiconductor substrate; and a charging protection portion sharing the capacitor insulator film and the upper electrode. The lower electrode is electrically connected through a first contact plug provided in the inter-layer insulator film finally to a first diffused layer formed in the semiconductor substrate surface, the capacitor insulator film of the charging protection portion is adhered to a second contact plug provided in the inter-layer insulator film, the contact plug is electrically connected finally to a second diffused layer formed in the semiconductor substrate surface, and the lower electrode is made of a first conductive material and the first and second contact plugs are made of a second conductive material different from the first conductive material.

摘要翻译： 本发明的半导体器件包括由半导体衬底上的层间绝缘膜上依次堆叠的下电极，电容绝缘膜和上电极构成的电容部， 以及共用电容绝缘膜和上电极的充电保护部。 下部电极通过设置在层间绝缘体膜中的第一接触插塞电连接到形成在半导体衬底表面中的第一扩散层，充电保护部分的电容器绝缘膜粘附到设置在 层间绝缘体膜，接触插塞最终电连接到形成在半导体衬底表面中的第二扩散层，下电极由第一导电材料制成，第一和第二接触插塞由第二导电 材料与第一导电材料不同。

公开(公告)号：US06350647B2

公开(公告)日：2002-02-26

申请号：US09772981

申请日：2001-01-31

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L27/10852 ,  H01L28/91

摘要： A plurality of charge storage electrodes are formed on an interlayer insulating film which is formed on a silicon substrate. A plurality of insulating members which surround periphery of the charge storage electrodes and which are separated from each other are formed. A capacitance insulating film is so formed as to cover the plurality of charge storage electrodes and the plurality of insulating members. A plate electrode is formed on the capacitance insulating film. The insulating members are formed of a silicon nitride film which has a function as an etching stopper for protecting the interlayer insulating film.

摘要翻译： 多个电荷存储电极形成在形成在硅衬底上的层间绝缘膜上。 形成围绕电荷存储电极的周围并且彼此分离的多个绝缘构件。 电容绝缘膜形成为覆盖多个电荷存储电极和多个绝缘构件。 在电容绝缘膜上形成平板电极。 绝缘构件由具有作为用于保护层间绝缘膜的蚀刻停止器的功能的氮化硅膜形成。

公开(公告)号：US5728616A

公开(公告)日：1998-03-17

申请号：US601502

申请日：1996-02-14

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92

CPC分类号： H01L28/55 ,  H01L27/10808 ,  H01L28/40

摘要： There is provided a semiconductor device, including: a semiconductor substrate having a major surface; a first insulating film formed on the major surface of the semiconductor substrate; a plurality of first conductive members spaced apart from each other on the first insulating film and formed to be connected to the semiconductor substrate; a plurality of storage electrodes formed on the first insulating film at positions respectively corresponding to the first conductive members; a plurality of high-permittivity films respectively stacked on the plurality of storage electrodes; a plurality of first counter electrodes respectively stacked on the plurality of high-permittivity films; a second insulating film, having a permittivity much lower than a permittivity of each of the high-permittivity films, for insulating the first conductive members, the high-permittivity films, and the first counter electrodes, respectively; and a second counter electrode, formed on the second insulating film, for connecting adjacent first counter electrodes on an upper surface of the second counter electrode, and a method of manufacturing the semiconductor device.

摘要翻译： 提供了一种半导体器件，包括：具有主表面的半导体衬底; 形成在所述半导体衬底的主表面上的第一绝缘膜; 多个第一导电构件，其在所述第一绝缘膜上彼此间隔开并形成为连接到所述半导体衬底; 多个存储电极，形成在分别对应于第一导电部件的位置处的第一绝缘膜上; 分别堆叠在所述多个存储电极上的多个高电容率膜; 分别堆叠在所述多个高介电常数膜上的多个第一对置电极; 第二绝缘膜，具有比每个高电容率膜的介电常数低得多的介电常数，分别用于绝缘第一导电构件，高电容率膜和第一对置电极; 以及第二对置电极，形成在所述第二绝缘膜上，用于连接所述第二对置电极的上表面上的相邻的第一对置电极，以及制造所述半导体器件的方法。

公开(公告)号：US06483194B2

公开(公告)日：2002-11-19

申请号：US09801679

申请日：2001-03-09

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L2348

CPC分类号： H01L27/10852 ,  H01L21/76804 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric, an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening. The lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate. A conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.

摘要翻译： 半导体器件包括半导体衬底，覆盖半导体衬底的第一层间电介质膜，覆盖第一层间电介质的第二层间电介质膜，具有穿过第二层间电介质膜的上层开口的开口，以及下层开口 将第一层间绝缘膜穿透到半导体衬底的表面并连接到上层开口。 下层开口被布置成使得下层的直径从上层开口朝向半导体衬底逐渐减小。 至少覆盖下层开口的底面和下层开口和上层开口的侧壁的导电膜。