公开(公告)号：US20110084755A1

公开(公告)日：2011-04-14

申请号：US12971510

申请日：2010-12-17

申请人： Yoshitsugu Inagaki ,  Koji Oka ,  Toshiaki Ozeki ,  Takeshi Okumoto

发明人： Yoshitsugu Inagaki ,  Koji Oka ,  Toshiaki Ozeki ,  Takeshi Okumoto

IPC分类号： H03K17/687

CPC分类号： H03K17/16 ,  G11C27/024 ,  H03K2217/0018 ,  H03K2217/0036 ,  H03M1/1245

摘要： An analog switch (100) of the present invention is characterized by being constructed by MOS transistors and comprising a switch (102) connecting an input terminal VIN(104) and the substrate voltage of the NMOS transistor (101), a switch (103), being operated in a reverse phase to that of the switch (102), connecting the substrate voltage of the NMOS transistor(101) and the ground (VSS), and a voltage follower circuit (106) which, having a high input impedance and being connected between the input terminal (104) and the switch (102), suppresses the flow of the input current from the input terminal (104). According to the present invention, in an analog switch which is constituted by MOS transistors, it is possible to suppress that the input current flows into the substrate when the analog switch repeats the ON state and the OFF state.

摘要翻译： 本发明的模拟开关（100）的特征在于由MOS晶体管构成，包括连接输入端子VIN（104）和NMOS晶体管（101）的衬底电压的开关（102），开关（103） ，与所述开关（102）的反相工作，连接所述NMOS晶体管（101）和所述地（VSS）的衬底电压，以及电压跟随器电路（106），所述电压跟随器电路具有高输入阻抗和 连接在输入端（104）和开关（102）之间，抑制来自输入端（104）的输入电流的流动。 根据本发明，在由MOS晶体管构成的模拟开关中，当模拟开关重复接通状态和断开状态时，可以抑制输入电流流入基板。

公开(公告)号：US20080158035A1

公开(公告)日：2008-07-03

申请号：US11964943

申请日：2007-12-27

申请人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

发明人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H03M1/12 ,  G06F1/04 ,  H03K3/356

CPC分类号： H03M1/0624 ,  G06F1/06 ,  H03K5/151 ,  H03M1/1215

摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

摘要翻译： 第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子 到第一D输入端，并将信号输出到第一D输入端作为反馈。 第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器 基于时钟信号输出。 第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为 基于时钟信号的第二输出。 第一输出和第二输出具有在相同定时反转的信号波形。

公开(公告)号：US20100117879A1

公开(公告)日：2010-05-13

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/36

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters (121,122), has a function of setting plural unit A/D converters which perform parallel processings according to a system request, and when the A/D converter is operated with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter (122) is halted by a control signal (15), thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： 通过使用第一和第二流水线型单元A / D转换器（121,122）对模拟输入信号进行时分并行处理，将模拟输入信号转换为数字输出信号的A / D转换器具有设定多个单元 A / D转换器，其根据系统请求执行并行处理，当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器（122）通过控制 信号（15），从而减少单元A / D转换器之间的通道间误差，提高A / D转换器的精度。

公开(公告)号：US07649487B2

公开(公告)日：2010-01-19

申请号：US11631844

申请日：2006-03-24

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US08004446B2

公开(公告)日：2011-08-23

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/38

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： A / D转换器，其通过使用第一和第二流水线型单元A / D转换器对模拟输入信号执行时分并行处理，将模拟输入信号转换为数字输出信号。 A / D转换器根据系统请求设置多个单元A / D转换器，执行并行处理，使得当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器 被控制信号停止，从而减少单元A / D转换器之间的通道间误差，以提高A / D转换器的精度。

公开(公告)号：US07884750B2

公开(公告)日：2011-02-08

申请号：US12643613

申请日：2009-12-21

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US20090040088A1

公开(公告)日：2009-02-12

申请号：US11631844

申请日：2006-03-24

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US20110254125A1

公开(公告)日：2011-10-20

申请号：US12600094

申请日：2008-05-16

申请人： Daisuke Nomasaki ,  Koji Oka ,  Toshiaki Ozeki

发明人： Daisuke Nomasaki ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H01L27/00

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2224/05553 ,  H01L2224/06 ,  H01L2924/0002 ,  H03H11/04 ,  H03H2001/0014 ,  H03L7/0891 ,  H03L7/093 ,  H01L2924/00

摘要： A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.

摘要翻译： 根据本发明的半导体集成电路配备有具有梳状电容器（10）的多个模拟宏，每个梳状电容器（10）具有梳状的第一电极（11）和梳状的第二电极（12） 电极（11）的梳齿部（13）和电极（12）的梳齿部（14）接合，使得梳齿部（13）和梳齿部（14）交替平行配置 并且梳状电容器的梳齿间隔S根据指示实际电容值和理想电容值之间的误差的绝对精度或指示相邻梳状电容器之间的电容值差的相对精度而变化。 因此，可以提供一种半导体集成电路，其配备有高精度模拟宏和具有确保高电容精度的梳状电容器的高度集成的模拟宏。

公开(公告)号：US07609194B2

公开(公告)日：2009-10-27

申请号：US11964943

申请日：2007-12-27

申请人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

发明人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H03M1/12

CPC分类号： H03M1/0624 ,  G06F1/06 ,  H03K5/151 ,  H03M1/1215

摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

摘要翻译： 第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子 到第一D输入端，并将信号输出到第一D输入端作为反馈。 第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器 基于时钟信号输出。 第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为 基于时钟信号的第二输出。 第一输出和第二输出具有在相同定时反转的信号波形。

公开(公告)号：US08567768B2

公开(公告)日：2013-10-29

申请号：US12781264

申请日：2010-05-17

申请人： Yoshihiro Iwata ,  Toshiaki Ozeki

发明人： Yoshihiro Iwata ,  Toshiaki Ozeki

IPC分类号： B01F3/04

CPC分类号： F28B3/04 ,  F28B9/04 ,  F28B9/10 ,  F28F9/22

摘要： In one embodiment, a direct-contact steam condenser includes: a steam cooling chamber; a inflow part; a plurality of first spray nozzles; and a water reservoir part. The inflow part leads turbine exhaust gas containing steam and non-condensable gas in a substantially horizontal direction into the steam cooling chamber. The plurality of first spray nozzles are disposed in the steam cooling chamber to be connected to a plurality of spray pipes extending along the direction in which the turbine exhaust gas is led in, and spray cooling water to the turbine exhaust gas. The water reservoir part is disposed under the steam cooling chamber to store condensate water that is condensed from the steam by the spraying of the cooling water.

摘要翻译： 在一个实施例中，直接接触蒸汽冷凝器包括：蒸汽冷却室; 流入部分 多个第一喷嘴; 和水库部分。 流入部分将包含蒸汽和不可冷凝气体的涡轮废气在基本上水平的方向引导到蒸汽冷却室中。 所述多个第一喷嘴设置在所述蒸汽冷却室中，以连接到沿着所述涡轮废气被引导的方向延伸的多个喷射管，并且将冷却水喷射到所述涡轮废气。 储水部分设置在蒸汽冷却室下方，以储存通过喷射冷却水从蒸汽冷凝的冷凝水。