公开(公告)号：US07391260B2

公开(公告)日：2008-06-24

申请号：US11510403

申请日：2006-08-25

申请人： Young Ho Kim ,  Mun Yang Park ,  Hyun Kyu Yu

发明人： Young Ho Kim ,  Mun Yang Park ,  Hyun Kyu Yu

IPC分类号： H03F1/36 ,  H03F3/45

CPC分类号： H03G1/007 ,  H03F1/08 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/381 ,  H03F2203/45138 ,  H03F2203/45522 ,  H03F2203/45524

摘要： An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside. According to the VGA, it is possible to provide a characteristic of linear variation of gain on a logarithmic scale with respect to a control voltage with a simple and inexpensive constitution. In addition, the VGA can be designed for a low pass filter having a conventional OTA used for a core circuit, and has a simple circuit structure. Therefore, the VGA is convenient for high integration and low-power design, and thus is appropriate for a terminal chip and so forth.

摘要翻译： 提供了调整移动通信系统的信号电平的模拟可变增益放大器（VGA）。 更具体地，公开了使用具有宽线性输入/输出范围的运算跨导放大器（OTA）的VGA的设计。 VGA包括两个双差分对OTA和反馈电阻。 第一双差分对OTA的第一差分输入接收来自前级的输入信号，并且第二差分输入通过差分输出和无源电阻负反馈。 其中连接结构的第一块和第二双差分对OTA的第一和第二差分输入相连接的输入端接收第一块级的输出信号。 输出通过可变电阻串联负反馈，其电阻随外部调整电压呈指数变化。 根据VGA，可以以简单且便宜的结构提供相对于控制电压的对数标度的增益的线性变化的特性。 此外，VGA可以设计用于具有用于核心电路的常规OTA的低通滤波器，并且具有简单的电路结构。 因此，VGA对于高集成度和低功耗设计是方便的，因此适用于终端芯片等。

公开(公告)号：US20070126501A1

公开(公告)日：2007-06-07

申请号：US11510403

申请日：2006-08-25

申请人： Young Ho Kim ,  Mun Yang Park ,  Hyun Kyu Yu

发明人： Young Ho Kim ,  Mun Yang Park ,  Hyun Kyu Yu

IPC分类号： H03F1/36

CPC分类号： H03G1/007 ,  H03F1/08 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/381 ,  H03F2203/45138 ,  H03F2203/45522 ,  H03F2203/45524

摘要： An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside. According to the VGA, it is possible to provide a characteristic of linear variation of gain on a logarithmic scale with respect to a control voltage with a simple and inexpensive constitution. In addition, the VGA can be designed for a low pass filter having a conventional OTA used for a core circuit, and has a simple circuit structure. Therefore, the VGA is convenient for high integration and low-power design, and thus is appropriate for a terminal chip and so forth.

摘要翻译： 提供了调整移动通信系统的信号电平的模拟可变增益放大器（VGA）。 更具体地，公开了使用具有宽线性输入/输出范围的运算跨导放大器（OTA）的VGA的设计。 VGA包括两个双差分对OTA和反馈电阻。 第一双差分对OTA的第一差分输入接收来自前级的输入信号，并且第二差分输入通过差分输出和无源电阻负反馈。 其中连接结构的第一块和第二双差分对OTA的第一和第二差分输入相连接的输入端接收第一块级的输出信号。 输出通过可变电阻串联负反馈，其电阻随外部调整电压呈指数变化。 根据VGA，可以以简单且便宜的结构提供相对于控制电压的对数标度的增益的线性变化的特性。 此外，VGA可以设计用于具有用于核心电路的常规OTA的低通滤波器，并且具有简单的电路结构。 因此，VGA对于高集成度和低功耗设计是方便的，因此适用于终端芯片等。

公开(公告)号：US20130063199A1

公开(公告)日：2013-03-14

申请号：US13615423

申请日：2012-09-13

申请人： Seon-Ho HAN ,  Hyun Ho Boo ,  Mun Yang Park ,  Jang Hong Choi ,  Hyun Kyu Yu

发明人： Seon-Ho HAN ,  Hyun Ho Boo ,  Mun Yang Park ,  Jang Hong Choi ,  Hyun Kyu Yu

IPC分类号： G06G7/14

CPC分类号： H03D7/165

摘要： Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.

摘要翻译： 公开了一种可编程复合混合器。 根据本发明的实施例，可以通过在复合混频器中编程内部信号的路径和符号来控制输出，以减少收发器中的处理带宽，功耗和芯片面积，从而提高 收发器

公开(公告)号：US09294135B2

公开(公告)日：2016-03-22

申请号：US13609638

申请日：2012-09-11

申请人： Ik Soo Eo ,  Sang-Kyun Kim ,  Mun Yang Park ,  Seon-Ho Han ,  Hyun Kyu Yu

发明人： Ik Soo Eo ,  Sang-Kyun Kim ,  Mun Yang Park ,  Seon-Ho Han ,  Hyun Kyu Yu

IPC分类号： H04B1/00

CPC分类号： H04B1/0021

摘要： A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.

摘要翻译： 数字RF接收机根据用于多模式接收，MIMO接收和带宽扩展接收的模式和频带不使用单独的接收机，并且仅改变单个接收机结构中的设置变量以便实现多模式接收， MIMO接收，带宽扩展接收和/或同时多模式操作，从而可以减少接收机的复杂性，开发成本和功耗。

公开(公告)号：US08295405B2

公开(公告)日：2012-10-23

申请号：US12629018

申请日：2009-12-01

申请人： Hyun Kyu Yu ,  Mun Yang Park ,  Jae Hoon Shim

发明人： Hyun Kyu Yu ,  Mun Yang Park ,  Jae Hoon Shim

IPC分类号： H04L27/22

CPC分类号： H04L27/3863

摘要： There is provided an apparatus and method for In-phase/Quadrature-phase (I/Q) mismatch calibration. The apparatus includes: a symmetrical point extracting part receiving continuous wave signals and extracting an I/Q channel average locus of the continuous wave signals; an error extracting part extracting a degree of distortion of the continuous wave signals from the extracted I/Q channel average locus; and a calibrating part calibrating a mismatch between I-channel signals and Q-channel signals of the continuous wave signals using the degree of distortion of the continuous wave signals.

摘要翻译： 提供了用于同相/正交相（I / Q）不匹配校准的装置和方法。 该装置包括：对称点提取部分，接收连续波信号并提取连续波信号的I / Q信道平均轨迹; 从所提取的I / Q通道平均轨迹提取连续波信号的失真程度的误差提取部分; 以及使用连续波信号的失真程度来校准连续波信号的I信道信号和Q信道信号之间的失配的校准部分。

公开(公告)号：US07626476B2

公开(公告)日：2009-12-01

申请号：US11690219

申请日：2007-03-23

申请人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

发明人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

IPC分类号： H01P3/08

CPC分类号： H01P3/003

摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

摘要翻译： 提供了一种使用多层互连CMOS技术的共面波导CPW。 在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到 最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。 结果，可以提高超高频电路的性能并使电路小型化。

公开(公告)号：US08542773B2

公开(公告)日：2013-09-24

申请号：US12968731

申请日：2010-12-15

申请人： Hyun Kyu Yu ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

发明人： Hyun Kyu Yu ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

IPC分类号： H04L27/20 ,  H03C3/00 ,  H03M3/00 ,  H03M1/66

CPC分类号： H03M1/68 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747 ,  H03M3/50

摘要： A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

摘要翻译： 提供数字RF转换器，数字RF调制器和发射器。 该数字RF转换器包括一个Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号之间产生对应于最低有效n比特的当前幅度，最低有效位（LSB）子块， 以低于第一采样速度的第二采样速度产生对应于输入信号中的中间k位的电流幅度，以及最高有效位（MSB）子块，其产生对应于最高有效m位的当前幅度 以第二采样速度输入信号。

公开(公告)号：US08013641B1

公开(公告)日：2011-09-06

申请号：US13098332

申请日：2011-04-29

申请人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03B21/00

CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

公开(公告)号：US06615398B2

公开(公告)日：2003-09-02

申请号：US10017315

申请日：2001-12-18

申请人： Hyun Kyu Yu ,  Seon-Ho Han ,  Mun Yang Park ,  Seong-Do Kim ,  Yong-Sik Youn ,  Lee-Sup Kim ,  Ki-Hyuk Sung ,  Byung-Do Yang ,  Young-Jun Kim

发明人： Hyun Kyu Yu ,  Seon-Ho Han ,  Mun Yang Park ,  Seong-Do Kim ,  Yong-Sik Youn ,  Lee-Sup Kim ,  Ki-Hyuk Sung ,  Byung-Do Yang ,  Young-Jun Kim

IPC分类号： G06F1750

CPC分类号： G06F1/0356 ,  G06F1/0328 ,  G06F2101/04 ,  G11C17/00

摘要： The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

公开(公告)号：US07956658B2

公开(公告)日：2011-06-07

申请号：US12607395

申请日：2009-10-28

申请人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。