公开(公告)号：US06627976B1

公开(公告)日：2003-09-30

申请号：US09687331

申请日：2000-10-13

申请人： Young Suk Chung ,  Hyung Ju Lee ,  Jae Hak Yee

发明人： Young Suk Chung ,  Hyung Ju Lee ,  Jae Hak Yee

IPC分类号： H01L23495

CPC分类号： H01L23/49548 ,  H01L21/565 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

摘要： The invention relates to a leadframe for semiconductor packages and a mold for molding the semiconductor package. The leadframe of the invention reduces occurrences of chip-out and floating of a chip paddle upon singulation after encapsulation. The leadframe inner voids define a chip paddle. At least one end of an inner void extends outwardly beyond a dam bar to provide a flow under pathway for encapsulating material when the leadframe is engaged by a top mold. The top mold has a sill that is continuous, e.g. tetragonal in shape, such that encapsulating material must flow under the sill when the top mold is clamping the leadframe. Encapsulating material is flowed into a mold gate of the leadframe and under a portion of the sill to engulf the semiconductor chip within the cavity formed by the top mold and the leadframe.

摘要翻译： 本发明涉及用于半导体封装的引线框和用于模制半导体封装的模具。 本发明的引线框架在封装之后可以减少芯片划片片的划分和漂浮。 引线框内部空隙定义了芯片桨。 内部空隙的至少一个端部向外延伸超过坝条，以在引线框架由顶部模具接合时提供用于封装材料的路径下的流动。 顶模具有连续的门槛，例如 四边形形状，使得当顶模夹紧引线框时，封装材料必须在基台下方流动。 封装材料流入引线框架的模具浇口并且在基底的一部分下方，以将由半模和引线框架形成的空腔中的半导体芯片填充。

公开(公告)号：US06525406B1

公开(公告)日：2003-02-25

申请号：US09687049

申请日：2000-10-13

申请人： Young Suk Chung ,  Sung Sik Jang ,  Jae Jin Lee ,  Tae Heon Lee ,  Hyung Ju Lee ,  Jung Woo Lee ,  Mu Hwan Seo ,  Jae Hak Yee ,  Ku Sun Hong

发明人： Young Suk Chung ,  Sung Sik Jang ,  Jae Jin Lee ,  Tae Heon Lee ,  Hyung Ju Lee ,  Jung Woo Lee ,  Mu Hwan Seo ,  Jae Hak Yee ,  Ku Sun Hong

IPC分类号： H01L23495

CPC分类号： H01L23/544 ,  H01L21/4842 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor package and a method for manufacturing the same. A planar or substantially planar die pad is disposed within a leadframe and is connected to the leadframe by a plurality of tie bars. An perimeter of an upper and lower surface of the die pad is half-etched to increase the moisture-permeation path of the finished package. A plurality of rectangular leads extends from the leadframe toward the die pad without contacting the die pad. A silver-plating layer may be formed on the upper surface of the leadframe. A semiconductor chip is mounted on the upper surface of the die pad in the leadframe. After deflashing, the package is treated with a sulfuric (H2SO4)-based solution to restore the internal leads to their original color. Prior to singulation, the externally exposed bottom surfaces of the leads are plated with copper, gold, solder, tin, nickel, palladium, or an alloy thereof to form a predetermined thickness of a plating layer. The singulation step comprises forming a burr at a peripheral side surface of the leads in the upward direction. The finished package may be marked with a recognition mark to enable a user to more easily identify the first lead.

摘要翻译： 公开了一种半导体封装及其制造方法。 平面或基本上平面的管芯焊盘设置在引线框架内，并且通过多个连接条连接到引线框架。 芯片焊盘的上表面和下表面的周边被半蚀刻以增加成品封装的透湿路径。 多个矩形引线从引线框架朝向管芯焊盘延伸，而不接触管芯焊盘。 可以在引线框架的上表面上形成镀银层。 半导体芯片安装在引线框架中的管芯焊盘的上表面上。 在消融后，将包装用硫酸（H 2 SO 4）的溶液处理，以将内部引线恢复到其原始颜色。 在分割之前，引线的外露的底表面镀有铜，金，焊料，锡，镍，钯或其合金，以形成预定厚度的镀层。 分割步骤包括在引线的周向侧表面沿向上方向形成毛刺。 完成的包装可以标记有识别标记，以使用户能够更容易地识别第一个引线。

公开(公告)号：US06469369B1

公开(公告)日：2002-10-22

申请号：US09607778

申请日：2000-06-30

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L23495

CPC分类号： H01L21/565 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2924/01005 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/00

摘要： A leadframe having a mold inflow groove provides for an increase in the number of inner leads for connecting with outer electrical sources and accurate singulation. A molding compound is introduced through mold inflow grooves positioned at both sides of a tie bar into the cavity so that no culls remain on the tie bar after molding. The end of a runner of the mold die is positioned at a sufficient distance away from the molding area of the leadframe to allow the top and bottom surfaces of the tie bar to remain free of culls.

摘要翻译： 具有模具流入槽的引线框架提供用于与外部电源连接的内部引线的数量的增加和精确的分割。 通过位于连接杆两侧的模具流入槽将模塑料引入空腔中，使得成型后在连杆上不会有剔除。 模具的浇道的端部定位在距离引线框架的模制区域足够的距离处，以允许连接杆的顶部和底部表面保持没有剔除。

公开(公告)号：US08102037B2

公开(公告)日：2012-01-24

申请号：US13036359

申请日：2011-02-28

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

摘要翻译： 一种半导体封装，其包括引线框架，所述引线框架包括框架，所述框架包括接地环和位于其中的芯片安装板。 在接地环和芯片安装板之间的延伸是多个细长的槽或孔。 接地环形成为在其底表面内包括形成厚度减小的区域的凹部。 结合到芯片安装板的半导体芯片可以经由导线与引线框架的引线和接地环电连接。 延伸到接地环的那些导线在其顶表面上结合在与底表面内的凹槽不对齐的位置，即最大厚度的接地环的那些区域。

公开(公告)号：US07928542B2

公开(公告)日：2011-04-19

申请号：US12399600

申请日：2009-03-06

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/34

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

摘要翻译： 一种半导体封装，其包括引线框架，所述引线框架包括框架，所述框架包括接地环和位于其中的芯片安装板。 在接地环和芯片安装板之间的延伸是多个细长的槽或孔。 接地环形成为在其底表面内包括形成厚度减小的区域的凹部。 结合到芯片安装板的半导体芯片可以经由导线与引线框架的引线和接地环电连接。 延伸到接地环的那些导线在其顶表面上结合在与底表面内的凹槽不对齐的位置，即最大厚度的接地环的那些区域。

公开(公告)号：US20090166842A1

公开(公告)日：2009-07-02

申请号：US12399600

申请日：2009-03-06

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

摘要翻译： 一种半导体封装，其包括引线框架，所述引线框架包括框架，所述框架包括接地环和位于其中的芯片安装板。 在接地环和芯片安装板之间的延伸是多个细长的槽或孔。 接地环形成为在其底表面内包括形成厚度减小的区域的凹部。 结合到芯片安装板的半导体芯片可以经由导线与引线框架的引线和接地环电连接。 延伸到接地环的那些导线在其顶表面上结合在与底表面内的凹槽不对齐的位置，即最大厚度的接地环的那些区域。

公开(公告)号：US07170150B2

公开(公告)日：2007-01-30

申请号：US10774893

申请日：2004-02-09

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L23/495 ,  H01L23/34

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

摘要翻译： 一种半导体封装，其包括引线框架，所述引线框架包括框架，所述框架包括接地环和位于其中的芯片安装板。 在接地环和芯片安装板之间的延伸是多个细长的槽或孔。 接地环形成为在其底表面内包括形成厚度减小的区域的凹部。 结合到芯片安装板的半导体芯片可以经由导线与引线框架的引线和接地环电连接。 延伸到接地环的那些导线在其顶表面上结合在与底表面内的凹槽不对齐的位置，即最大厚度的接地环的那些区域。

公开(公告)号：US06713322B2

公开(公告)日：2004-03-30

申请号：US10013160

申请日：2001-12-10

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L23495

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

公开(公告)号：US07521294B2

公开(公告)日：2009-04-21

申请号：US11510544

申请日：2006-08-25

申请人： Hyung Ju Lee

发明人： Hyung Ju Lee

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

公开(公告)号：US06616436B1

公开(公告)日：2003-09-09

申请号：US09687126

申请日：2000-10-13

申请人： Hyung Ju Lee ,  Ku Sun Hong ,  Jae Hun Ku

发明人： Hyung Ju Lee ,  Ku Sun Hong ,  Jae Hun Ku

IPC分类号： B29C4514

CPC分类号： B29C45/14655 ,  B29C45/2701 ,  B29C45/40 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A mold for manufacturing semiconductor packages, which allows leadframes to be easily separated from a top mold section after a molding process by utilizing eject pins therein. The mold includes a bottom mold section having housing parts on the upper surface so as to allow leadframes to be placed in a flat state therein, and a top mold formed with transports therethrough. The top mold also incorporates runners formed along a lower surface with connections to the transports to introduce encapsulation material into select regions. A plurality of gates and cavities for molding the semiconductor packages are in flow communication. The eject pins are reciprocally mounted in the top mold section contiguous with the runners thereof to facilitate separation of the leadframes from the top mold.

摘要翻译： 一种用于制造半导体封装的模具，其通过在其中利用弹出销，使得引线框架在模制过程之后容易地与顶模部分分离。 模具包括底部模具部分，其具有在上表面上的壳体部分，以便允许引线框架处于平坦状态;以及顶部模具，其形成有传送通过。 顶部模具还包括沿着下表面形成的流道，连接到输送机以将包封材料引入选择区域。 用于模制半导体封装的多个栅极和空腔是流动连通的。 弹出销相互安装在与其滑动件邻接的顶部模具部分中，以便引导框架与顶部模具分离。