公开(公告)号：US08343820B2

公开(公告)日：2013-01-01

申请号：US12624966

申请日：2009-11-24

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed.

摘要翻译： 一种用于制造垂直沟道型非易失性存储器件的方法，包括沿着从衬底突出的通道堆叠的多个存储单元，包括：在衬底上交替地形成多个第一材料层和多个第二材料层; 在所述基板上形成有多个第一材料层和形成在其上的多个第二材料层的缓冲层; 通过蚀刻缓冲层，多个第二材料层和多个第一材料层形成沟槽; 在衬底上形成用于沟道的材料层以填充沟槽; 以及通过进行平坦化处理直到缓冲层的表面露出来形成通道。

公开(公告)号：US07998816B2

公开(公告)日：2011-08-16

申请号：US12494782

申请日：2009-06-30

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.

摘要翻译： 一种制造半导体器件的方法包括：通过衬底中的沟槽形成彼此分离的掩埋位线，形成暴露衬底顶表面的多个第一柱孔，形成埋在第一柱孔中的第一活性柱， 在包括第一活性柱的所得结构的整个表面上形成栅极导电层，通过蚀刻栅极导电层以覆盖第一有源支柱形成栅极电极，形成多个第二柱状孔，其部分地暴露第一活性柱 蚀刻栅电极，以及形成埋在第二柱孔中并连接到第一活动柱的第二活性柱。

公开(公告)号：US07989292B2

公开(公告)日：2011-08-02

申请号：US12334324

申请日：2008-12-12

申请人： Sang-Hoon Cho ,  Yun-Seok Cho ,  Myung-Ok Kim ,  Sang-Hoon Park ,  Young-Kyun Jung

发明人： Sang-Hoon Cho ,  Yun-Seok Cho ,  Myung-Ok Kim ,  Sang-Hoon Park ,  Young-Kyun Jung

IPC分类号： H01L21/336

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

摘要翻译： 在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层 在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层 ，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。 在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

公开(公告)号：US07939411B2

公开(公告)日：2011-05-10

申请号：US12493174

申请日：2009-06-27

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L21/336

CPC分类号： H01L27/10885 ,  H01L27/10876

摘要： A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars.

摘要翻译： 一种制造半导体器件的方法包括在第一衬底中形成掩埋位线; 形成将埋置的位线彼此分离的沟槽; 形成层间绝缘层以间隙填充沟槽; 在填充有所述层间绝缘层的所述第一衬底间隙上形成第二衬底; 在所述第二基板上形成保护图案; 通过使用保护图案作为蚀刻阻挡层蚀刻第二基板来形成多个有源支柱; 并且形成围绕活动柱的侧壁的垂直门。

公开(公告)号：US08653575B2

公开(公告)日：2014-02-18

申请号：US13176321

申请日：2011-07-05

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L27/108

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.

摘要翻译： 一种制造半导体器件的方法包括：通过衬底中的沟槽形成彼此分离的掩埋位线，形成暴露衬底顶表面的多个第一柱孔，形成埋在第一柱孔中的第一活性柱， 在包括第一活性柱的所得结构的整个表面上形成栅极导电层，通过蚀刻栅极导电层以覆盖第一有源支柱形成栅极电极，形成多个第二柱状孔，其部分地暴露第一活性柱 蚀刻栅电极，以及形成埋在第二柱孔中并连接到第一活动柱的第二活性柱。

公开(公告)号：US07829415B2

公开(公告)日：2010-11-09

申请号：US12336369

申请日：2008-12-16

申请人： Yun-Seok Cho ,  Young-Kyun Jung ,  Chun-Hee Lee

发明人： Yun-Seok Cho ,  Young-Kyun Jung ,  Chun-Hee Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L29/7827

摘要： A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.

摘要翻译： 制造半导体器件的方法包括在衬底上形成多个柱状图案，用第一导电层填充柱状图案之间的间隙，在与一个方向相邻的柱状图案上形成第一硬掩模层图案，蚀刻第一 使用所述第一硬掩模层图案作为蚀刻阻挡层，在与所述一个方向交叉的另一个方向上相邻的所述柱图案上形成第二硬掩模图案，以及通过蚀刻所述第一导电层形成围绕所述柱图案的栅电极 使用第二硬掩模层图案蚀刻作为蚀刻阻挡层。

公开(公告)号：US20090242945A1

公开(公告)日：2009-10-01

申请号：US12318165

申请日：2008-12-23

申请人： Yun-Seok Cho ,  Sang-Hoon Park ,  Young-Kyun Jung ,  Chun-Hee Lee

发明人： Yun-Seok Cho ,  Sang-Hoon Park ,  Young-Kyun Jung ,  Chun-Hee Lee

IPC分类号： H01L29/78 ,  H01L21/4763

CPC分类号： H01L29/66666 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966

摘要： In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier.

摘要翻译： 在具有柱状图案的基板上制造半导体器件的方法中，在柱状图案上形成栅电极而不对其进行蚀刻。 导电图形填充在相邻的柱图案之间，在导电图案上方形成间隔物，并且在每个柱图案的周围形成围绕的侧壁，并且通过使用间隔物作为蚀刻阻挡层蚀刻导电图案来形成栅电极。

公开(公告)号：US07560327B2

公开(公告)日：2009-07-14

申请号：US11450658

申请日：2006-06-08

申请人： Kwang-Ok Kim ,  Young-Kyun Jung

发明人： Kwang-Ok Kim ,  Young-Kyun Jung

IPC分类号： H01L21/8238

CPC分类号： H01L21/28035 ,  H01L21/823842

摘要： A method for fabricating a semiconductor device with a dual gate structure is provided. The method includes: forming a gate oxide layer over a substrate; forming a gate conductive layer over the gate oxide layer; forming an amorphous carbon layer over the gate conductive layer; forming a photosensitive pattern over the amorphous carbon layer; etching the amorphous carbon layer using the photosensitive pattern as an etch mask to form a patterned amorphous carbon layer; performing an ion implantation process using the patterned amorphous carbon layer as an ion implantation barrier to implant an impurity onto the gate conductive layer; removing the patterned amorphous carbon layer; and patterning the gate conductive layer to form a gate structure.

摘要翻译： 提供一种制造具有双栅结构的半导体器件的方法。 该方法包括：在衬底上形成栅氧化层; 在所述栅极氧化物层上形成栅极导电层; 在所述栅极导电层上形成非晶碳层; 在所述无定形碳层上形成感光图案; 使用感光图案作为蚀刻掩模蚀刻非晶碳层以形成图案化的无定形碳层; 使用图案化的非晶碳层作为离子注入势垒进行离子注入工艺，以将杂质注入到栅极导电层上; 去除图案化的无定形碳层; 以及图案化栅极导电层以形成栅极结构。

公开(公告)号：US08524604B2

公开(公告)日：2013-09-03

申请号：US13301351

申请日：2011-11-21

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/1052

摘要： A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

摘要翻译： 一种形成精细图案的方法包括在目标层上依次形成第一薄膜和第二薄膜，用于图案化，在第二薄膜上形成隔板，在分隔壁的侧壁上形成间隔物之后移除隔板，形成第一图案 通过在暴露所述间隔物的同时蚀刻第一区域的第二薄膜和第二区域的第二薄膜来形成第二薄膜，通过使用间隔物作为掩模形成第二薄膜的第二图案，并蚀刻第二薄膜的第二图案 在第一区域中形成薄膜，通过使用第二薄膜的第一和第二图案作为第一和第二区域中的掩模形成第一薄膜图案，并蚀刻第一薄膜，并蚀刻图案目标层。

公开(公告)号：US08294207B2

公开(公告)日：2012-10-23

申请号：US13168301

申请日：2011-06-24

申请人： Sang-Hoon Cho ,  Yun-Seok Cho ,  Myung-Ok Kim ,  Sang-Hoon Park ,  Young-Kyun Jung

发明人： Sang-Hoon Cho ,  Yun-Seok Cho ,  Myung-Ok Kim ,  Sang-Hoon Park ,  Young-Kyun Jung

IPC分类号： H01L29/78

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

摘要翻译： 在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层 在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层 ，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。 在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。