公开(公告)号：US08766352B2

公开(公告)日：2014-07-01

申请号：US13218971

申请日：2011-08-26

申请人： Young Kyun Jung

发明人： Young Kyun Jung

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.

摘要翻译： 半导体器件包括形成在衬底上的管道沟道层，形成在管道沟道层上以将管道沟道层耦合到位线的第一垂直沟道层，在管道沟道层上形成的第二垂直沟道层，以耦合管道 沟道层到源极线，多层，包括电荷陷阱层并形成为围绕第一垂直沟道层，第二垂直沟道层和管道沟道层，形成为围绕多层的绝缘势垒层， 形成在管道沟道层和位线之间的多个第一导电层，其中第一垂直沟道层穿过第一导电层，以及形成在管道沟道层和源极线之间的多个第二导电层，其中， 第二垂直层通过第二导电层。

公开(公告)号：US08524604B2

公开(公告)日：2013-09-03

申请号：US13301351

申请日：2011-11-21

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/1052

摘要： A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

摘要翻译： 一种形成精细图案的方法包括在目标层上依次形成第一薄膜和第二薄膜，用于图案化，在第二薄膜上形成隔板，在分隔壁的侧壁上形成间隔物之后移除隔板，形成第一图案 通过在暴露所述间隔物的同时蚀刻第一区域的第二薄膜和第二区域的第二薄膜来形成第二薄膜，通过使用间隔物作为掩模形成第二薄膜的第二图案，并蚀刻第二薄膜的第二图案 在第一区域中形成薄膜，通过使用第二薄膜的第一和第二图案作为第一和第二区域中的掩模形成第一薄膜图案，并蚀刻第一薄膜，并蚀刻图案目标层。

公开(公告)号：US08294207B2

公开(公告)日：2012-10-23

申请号：US13168301

申请日：2011-06-24

申请人： Sang-Hoon Cho ,  Yun-Seok Cho ,  Myung-Ok Kim ,  Sang-Hoon Park ,  Young-Kyun Jung

发明人： Sang-Hoon Cho ,  Yun-Seok Cho ,  Myung-Ok Kim ,  Sang-Hoon Park ,  Young-Kyun Jung

IPC分类号： H01L29/78

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

摘要翻译： 在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层 在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层 ，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。 在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

公开(公告)号：US20120049267A1

公开(公告)日：2012-03-01

申请号：US13218971

申请日：2011-08-26

申请人： Young Kyun JUNG

发明人： Young Kyun JUNG

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.

摘要翻译： 半导体器件包括形成在衬底上的管道沟道层，形成在管道沟道层上以将管道沟道层耦合到位线的第一垂直沟道层，在管道沟道层上形成的第二垂直沟道层，以耦合管道 沟道层到源极线，多层，包括电荷陷阱层并形成为围绕第一垂直沟道层，第二垂直沟道层和管道沟道层，形成为围绕多层的绝缘势垒层， 形成在管道沟道层和位线之间的多个第一导电层，其中第一垂直沟道层穿过第一导电层，以及形成在管道沟道层和源极线之间的多个第二导电层，其中， 第二垂直层通过第二导电层。

公开(公告)号：US20100330411A1

公开(公告)日：2010-12-30

申请号：US12824564

申请日：2010-06-28

申请人： Sang Cheol NAM ,  Ho Young Park ,  Young Chang Lim ,  Ki Chang Lee ,  Young Kyun Jung

发明人： Sang Cheol NAM ,  Ho Young Park ,  Young Chang Lim ,  Ki Chang Lee ,  Young Kyun Jung

IPC分类号： H01M10/28 ,  H01M4/00 ,  H01M10/26

CPC分类号： H01M10/0436 ,  H01M2/08 ,  H01M2/22 ,  H01M4/661 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/0585 ,  Y10T29/49108

摘要： Provided is a thin film battery, including: a base substrate; a cathode current collector pattern and an anode current collector pattern being formed on the base substrate and being electrically separate from each other; a cathode terminal and an anode terminal being directly bonded with the cathode current collector pattern and the anode current collector pattern; a cathode and an anode being disposed on the cathode current collector pattern and the anode current collector pattern; and an electrolyte layer being disposed between the cathode and the anode.

摘要翻译： 提供一种薄膜电池，包括：基底; 阴极集电体图案和阳极集电体图案，其形成在基底基板上并且彼此电分离; 阴极端子和阳极端子与阴极集电体图案和阳极集电体图案直接接合; 阴极和阳极设置在阴极集电器图案和阳极集电器图案上; 并且设置在阴极和阳极之间的电解质层。

公开(公告)号：US20100124812A1

公开(公告)日：2010-05-20

申请号：US12493174

申请日：2009-06-27

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L21/768

CPC分类号： H01L27/10885 ,  H01L27/10876

摘要： A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars.

摘要翻译： 一种制造半导体器件的方法包括在第一衬底中形成掩埋位线; 形成将埋置的位线彼此分离的沟槽; 形成层间绝缘层以间隙填充沟槽; 在填充有所述层间绝缘层的所述第一衬底间隙上形成第二衬底; 在所述第二基板上形成保护图案; 通过使用保护图案作为蚀刻阻挡层蚀刻第二基板来形成多个有源支柱; 并且形成围绕活动柱的侧壁的垂直门。

公开(公告)号：US20090253236A1

公开(公告)日：2009-10-08

申请号：US12336369

申请日：2008-12-16

申请人： Yun-Seok CHO ,  Young-Kyun Jung ,  Chun-Hee Lee

发明人： Yun-Seok CHO ,  Young-Kyun Jung ,  Chun-Hee Lee

IPC分类号： H01L21/34

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L29/7827

摘要： A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.

摘要翻译： 制造半导体器件的方法包括在衬底上形成多个柱状图案，用第一导电层填充柱状图案之间的间隙，在与一个方向相邻的柱状图案上形成第一硬掩模层图案，蚀刻第一 使用所述第一硬掩模层图案作为蚀刻阻挡层，在与所述一个方向交叉的另一个方向上相邻的所述柱图案上形成第二硬掩模图案，以及通过蚀刻所述第一导电层形成围绕所述柱图案的栅电极 使用第二硬掩模层图案蚀刻作为蚀刻阻挡层。

公开(公告)号：US20080001190A1

公开(公告)日：2008-01-03

申请号：US11644883

申请日：2006-12-26

申请人： Young-Kyun Jung

发明人： Young-Kyun Jung

IPC分类号： H01L29/76

CPC分类号： H01L29/66651 ,  H01L29/66621

摘要： A semiconductor device with a recess gate includes a substrate, a semiconductive layer having an opening corresponding to a gate region, a gate electrode filled in the opening, and a gate insulating layer interposed between the gate electrode and the substrate, and between the gate electrode and the semiconductive layer.

摘要翻译： 具有凹槽的半导体器件包括衬底，具有对应于栅极区域的开口的半导体层，填充在开口中的栅极电极以及介于栅电极和衬底之间的栅极绝缘层，以及栅电极 和半导体层。

公开(公告)号：US20070148885A1

公开(公告)日：2007-06-28

申请号：US11450658

申请日：2006-06-08

申请人： Kwang-Ok Kim ,  Young-Kyun Jung

发明人： Kwang-Ok Kim ,  Young-Kyun Jung

IPC分类号： H01L21/336

CPC分类号： H01L21/28035 ,  H01L21/823842

摘要： A method for fabricating a semiconductor device with a dual gate structure is provided. The method includes: forming a gate oxide layer over a substrate; forming a gate conductive layer over the gate oxide layer; forming an amorphous carbon layer over the gate conductive layer; forming a photosensitive pattern over the amorphous carbon layer; etching the amorphous carbon layer using the photosensitive pattern as an etch mask to form a patterned amorphous carbon layer; performing an ion implantation process using the patterned amorphous carbon layer as an ion implantation barrier to implant an impurity onto the gate conductive layer; removing the patterned amorphous carbon layer; and patterning the gate conductive layer to form a gate structure.

摘要翻译： 提供一种制造具有双栅结构的半导体器件的方法。 该方法包括：在衬底上形成栅氧化层; 在所述栅极氧化物层上形成栅极导电层; 在所述栅极导电层上形成非晶碳层; 在所述无定形碳层上形成感光图案; 使用感光图案作为蚀刻掩模蚀刻非晶碳层以形成图案化的无定形碳层; 使用图案化的非晶碳层作为离子注入势垒进行离子注入工艺，以将杂质注入到栅极导电层上; 去除图案化的无定形碳层; 以及图案化栅极导电层以形成栅极结构。

公开(公告)号：US20050187322A1

公开(公告)日：2005-08-25

申请号：US11031786

申请日：2005-01-06

申请人： Eun Ha Park ,  Byung Hun Park ,  Young Kyun Jung ,  Young Moo Park ,  Soo Chul Park

发明人： Eun Ha Park ,  Byung Hun Park ,  Young Kyun Jung ,  Young Moo Park ,  Soo Chul Park

IPC分类号： B29C45/00 ,  B29C44/34 ,  B29K77/00 ,  B29L31/30 ,  C08K3/34 ,  C08K5/12 ,  C08K5/435 ,  C08K7/14 ,  C08L77/06 ,  C08K3/40 ,  C08K5/09

CPC分类号： B29C44/348 ,  C08J9/0023 ,  C08J9/0033 ,  C08J9/0066 ,  C08J9/0085 ,  C08J9/0095 ,  C08J9/122 ,  C08J2203/06 ,  C08J2203/08 ,  C08J2377/00

摘要： A polyamide resin composition for microcellular foaming injection molding relates to a polyamide resin composition including a polyamide resin, a glass fiber, a mineral, and sulfonamide-based or dicarboxylic acid-based plasticizer. The resin enables a decrease in the weight of the manufactured goods and improved surface properties without showing any defect, such as surface sink and flowmark, or any reinforcing materials, such as glass fiber and clay, on the surface, while elevating other physical properties such as heat resistance, fluidity, and rigidity.

摘要翻译： 用于微孔发泡注射成型的聚酰胺树脂组合物涉及包含聚酰胺树脂，玻璃纤维，矿物和磺酰胺类或二羧酸类增塑剂的聚酰胺树脂组合物。 该树脂能够降低制成品的重量并改善表面性能，而不会在表面上出现任何缺陷，例如表面沉积物和流动标记，或任何增强材料，例如玻璃纤维和粘土，同时提高其它物理性质 作为耐热性，流动性和刚性。