公开(公告)号：US20070013043A1

公开(公告)日：2007-01-18

申请号：US11302736

申请日：2005-12-13

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

摘要翻译： 提供了不具有芯的芯片封装，包括图案化电路层，芯片，焊接掩模，模塑料和多个外部端子。 图案化电路层具有彼此相对的第一表面和第二表面。 布置在第一表面上的芯片电连接到图案化电路层。 设置在第二表面上的焊料掩模具有多个第一开口，图案化电路层的一部分露出。 具有多个通孔的成型复合物覆盖图形电路层，并将芯片固定在图案化电路层上。 布置在通孔中的每个外部端子电连接到图案化电路层。

公开(公告)号：US20100187692A1

公开(公告)日：2010-07-29

申请号：US12756377

申请日：2010-04-08

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/498

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

摘要翻译： 提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。 该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层 被暴露。 芯片设置在第一表面上并且电连接到图案化电路层。 模塑料覆盖图案电路层并将芯片固定在图案化电路层上。 外部端子设置在第一开口中并电连接到图案化电路层。

公开(公告)号：US07436074B2

公开(公告)日：2008-10-14

申请号：US11302736

申请日：2005-12-13

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

摘要翻译： 提供了不具有芯的芯片封装，包括图案化电路层，芯片，焊接掩模，模塑料和多个外部端子。 图案化电路层具有彼此相对的第一表面和第二表面。 布置在第一表面上的芯片电连接到图案化电路层。 设置在第二表面上的焊料掩模具有多个第一开口，图案化电路层的一部分露出。 具有多个通孔的成型复合物覆盖图形电路层，并将芯片固定在图案化电路层上。 布置在通孔中的每个外部端子电连接到图案化电路层。

公开(公告)号：US07919874B2

公开(公告)日：2011-04-05

申请号：US12756377

申请日：2010-04-08

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

摘要翻译： 提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。 该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层 被暴露。 芯片设置在第一表面上并且电连接到图案化电路层。 模塑料覆盖图案电路层并将芯片固定在图案化电路层上。 外部端子设置在第一开口中并电连接到图案化电路层。

公开(公告)号：US20100187691A1

公开(公告)日：2010-07-29

申请号：US12756368

申请日：2010-04-08

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/498

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

公开(公告)号：US07723853B2

公开(公告)日：2010-05-25

申请号：US12196791

申请日：2008-08-22

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

摘要翻译： 提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。 该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层 被暴露。 芯片设置在第一表面上并且电连接到图案化电路层。 模塑料覆盖图案电路层并将芯片固定在图案化电路层上。 外部端子设置在第一开口中并电连接到图案化电路层。

公开(公告)号：US20080303174A1

公开(公告)日：2008-12-11

申请号：US12196791

申请日：2008-08-22

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/52

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

摘要翻译： 提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。 该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层 被暴露。 芯片设置在第一表面上并且电连接到图案化电路层。 模塑料覆盖图案电路层并将芯片固定在图案化电路层上。 外部端子设置在第一开口中并电连接到图案化电路层。

公开(公告)号：US20090189296A1

公开(公告)日：2009-07-30

申请号：US12275172

申请日：2008-11-20

申请人： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

发明人： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/3114 ,  H01L23/49517 ,  H01L23/49822 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

摘要翻译： 提供了一种倒装芯片四边形扁平无铅封装结构的制造方法。 首先在制造方法中设置具有多根引线的引线框架。 在引线框架上形成介电层，并使引线的顶表面和底表面露出。 在电介质层上形成包括多个焊盘的重分配层和连接焊盘和引线顶表面的多条导线。 形成阻焊层以覆盖再分布层，电介质层和引线，并露出焊盘的表面。 在阻焊层上形成粘接层。 提供具有多个凸块的芯片。 该芯片用粘合剂层粘附在阻焊层上，并且每个凸块与其中一个焊盘电连接。

公开(公告)号：US20080281999A1

公开(公告)日：2008-11-13

申请号：US11744961

申请日：2007-05-07

申请人： Hsin-Yu Kang ,  Cheng-Ting Wu

发明人： Hsin-Yu Kang ,  Cheng-Ting Wu

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In an electronic system, a DMA circuit is supplied with a device selection signal that indicates a processor is accessing or going to access a memory. If the DMA circuit finds that the processor is not accessing or not going to access the memory, the DMA circuit starts its DMA operations. Once the DMA circuit finds that the processor is going to access the memory, the DMA circuit stops its DMA operation and return the use of the memory to the processor.

摘要翻译： 在电子系统中，向DMA电路提供指示处理器正在访问或将访问存储器的设备选择信号。 如果DMA电路发现处理器没有访问或不访问存储器，DMA电路将启动其DMA操作。 一旦DMA电路发现处理器要访问存储器，DMA电路停止其DMA操作，并将存储器的使用返回给处理器。

公开(公告)号：US20080174031A1

公开(公告)日：2008-07-24

申请号：US11806023

申请日：2007-05-29

申请人： Hung-Tsun Lin ,  Wu-Chang Tu ,  Cheng-Ting Wu

发明人： Hung-Tsun Lin ,  Wu-Chang Tu ,  Cheng-Ting Wu

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/585 ,  H01L24/28 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

摘要翻译： IC封装主要包括基板，管芯安装层，芯片，至少一个接合线和多个电连接部件。 基板具有顶表面和底表面，其中顶表面包括用于设置管芯附接层的管芯附着区域。 芯片通过管芯附着层附接到管芯附着区域，并通过电连接部件与衬底电连接。 接合线的两端接合到基板的顶表面上的两个互连指状物，其中至少一部分接合线被封装在管芯附着层中以替代传统衬底内部的一些布线或通孔。 因此，衬底具有简单且降低的布线层，即降低衬底成本。 也显示了相应IC封装的芯片载体。