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    Quick-release fixing structure for electronic equipments
    1.
    发明授权
    Quick-release fixing structure for electronic equipments 有权
    电子设备快速固定结构

    公开(公告)号：US09161465B2

    公开(公告)日：2015-10-13

    申请号：US13529849

    申请日：2012-06-21

    Applicant: Chia-Jung Chen ,  Yu-Wei Lin

    Inventor： Chia-Jung Chen ,  Yu-Wei Lin

    IPC: H05K5/02 ,  F16B5/07 ,  F16B21/09

    CPC classification number: H05K5/0204 ,  F16B5/07 ,  F16B21/09 ,  Y10T403/32975

    Abstract: In a quick-release fixing structure for an electronic equipment, the electronic equipment includes a plurality of holes and a snap slot, and the quick-release fixing structure includes a substrate, a turning element and a plurality of fixing elements. The substrate includes a plurality of grooves and a port, and each groove includes a first groove hole and a second groove hole interconnected to the first groove hole, and the second groove hole is greater than the first groove hole. The turning element is coupled to the substrate and includes a bump exposed from the port and snapped into the snap slot. Each fixing element is passed through each first groove hole and fixed to each hole. The turning element can be turned to push the electronic equipment to move each fixing element into each second groove hole, and separate the electronic equipment from the substrate.

    Abstract translation: 在电子设备的快速释放固定结构中，电子设备包括多个孔和卡槽，并且快速释放固定结构包括基板，转动元件和多个固定元件。 基板包括多个槽和端口，每个槽包括与第一槽孔互连的第一槽孔和第二槽孔，第二槽孔大于第一槽孔。 旋转元件联接到基板并且包括从端口暴露并且卡扣到卡槽中的凸块。 每个固定元件通过每个第一槽孔并固定到每个孔。 可以转动转动元件以推动电子设备将每个固定元件移动到每个第二槽孔中，并将电子设备与基板分离。

    Calibration circuit and calibration method
    2.
    发明授权
    Calibration circuit and calibration method 有权
    校准电路和校准方法

    公开(公告)号：US08823388B2

    公开(公告)日：2014-09-02

    申请号：US13152284

    申请日：2011-06-03

    Applicant: Yu-Wei Lin

    Inventor： Yu-Wei Lin

    IPC: G01R35/00 ,  G01R23/175 ,  H03H7/32 ,  G01R31/317 ,  H03H11/26 ,  H03H7/01

    CPC classification number: H03H7/32 ,  G01R31/31725 ,  G01R35/00 ,  H03H7/0153 ,  H03H11/265 ,  H03H2210/043

    Abstract: A calibration circuit and a calibration method are provided. The calibration circuit has a delay circuit, a phase detector, and a controller. The delay circuit delays an input signal to output an output signal, wherein a delay time between the input signal and the output signal is related to an equivalent capacitance and an equivalent resistance of the delay circuit. The phase detector coupled to the delay circuit compares the phases of the input signal and the output signal. The controller coupled to the delay circuit and the phase detector generates a control signal according to the comparison result of the phase detector to adjust the equivalent resistance of the delay circuit.

    Abstract translation: 提供校准电路和校准方法。 校准电路具有延迟电路，相位检测器和控制器。 延迟电路延迟输入信号以输出输出信号，其中输入信号和输出信号之间的延迟时间与等效电容和延迟电路的等效电阻相关。 耦合到延迟电路的相位检测器比较输入信号和输出信号的相位。 耦合到延迟电路的控制器和相位检测器根据相位检测器的比较结果生成控制信号，以调整延迟电路的等效电阻。

    CALIBRATION CIRCUIT AND CALIBRATION METHOD
    3.
    发明申请
    CALIBRATION CIRCUIT AND CALIBRATION METHOD 有权
    校准电路和校准方法

    公开(公告)号：US20120306557A1

    公开(公告)日：2012-12-06

    申请号：US13152284

    申请日：2011-06-03

    Applicant: Yu-Wei Lin

    Inventor： Yu-Wei Lin

    IPC: H03H11/26

    CPC classification number: H03H7/32 ,  G01R31/31725 ,  G01R35/00 ,  H03H7/0153 ,  H03H11/265 ,  H03H2210/043

    Abstract: A calibration circuit and a calibration method are provided. The calibration circuit has a delay circuit, a phase detector, and a controller. The delay circuit delays an input signal to output an output signal, wherein a delay time between the input signal and the output signal is related to an equivalent capacitance and an equivalent resistance of the delay circuit. The phase detector coupled to the delay circuit compares the phases of the input signal and the output signal. The controller coupled to the delay circuit and the phase detector generates a control signal according to the comparison result of the phase detector to adjust the equivalent resistance of the delay circuit.

    Abstract translation: 提供校准电路和校准方法。 校准电路具有延迟电路，相位检测器和控制器。 延迟电路延迟输入信号以输出输出信号，其中输入信号和输出信号之间的延迟时间与等效电容和延迟电路的等效电阻相关。 耦合到延迟电路的相位检测器比较输入信号和输出信号的相位。 耦合到延迟电路的控制器和相位检测器根据相位检测器的比较结果生成控制信号，以调整延迟电路的等效电阻。

    Input common mode circuit
    5.
    发明授权
    Input common mode circuit 有权
    输入共模电路

    公开(公告)号：US08130036B2

    公开(公告)日：2012-03-06

    申请号：US12917652

    申请日：2010-11-02

    Applicant: Yu-Wei Lin ,  Yung-Chow Peng

    Inventor： Yu-Wei Lin ,  Yung-Chow Peng

    IPC: H03F3/45

    CPC classification number: H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2203/45512 ,  H03F2203/45588

    Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

    Abstract translation: 电路提供对应于差分输入Inn和Inp的第一电流，以及对应于共模输入Vcm的第二电流。 电路然后将差分电流和共模电流反射到第三电流和第四电流。 基于镜像差分电流和镜像共模电流之间的差异，电路拉起或拉下这些电流，以平衡差分输入和共模输入之间的相应差值。 实际上，该电路将输入共模电压调整到期望的电平，而不给它提供上升到不需要的电平的机会。

    Input common mode circuit
    9.
    发明授权
    Input common mode circuit 有权

    公开(公告)号：US08242842B2

    公开(公告)日：2012-08-14

    申请号：US13364043

    申请日：2012-02-01

    Applicant: Yu-Wei Lin ,  Yung-Chow Peng

    Inventor： Yu-Wei Lin ,  Yung-Chow Peng

    IPC: H03F3/45

    CPC classification number: H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2203/45512 ,  H03F2203/45588

    Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

    SIGNAL TRANSMISSION SYSTEM WITH CLOCK SIGNAL GENERATOR CONFIGURED FOR GENERATING CLOCK SIGNAL HAVING STEPWISE/SMOOTH FREQUENCY TRANSITION AND RELATED SIGNAL TRANSMISSION METHOD THEREOF
    10.
    发明申请
    SIGNAL TRANSMISSION SYSTEM WITH CLOCK SIGNAL GENERATOR CONFIGURED FOR GENERATING CLOCK SIGNAL HAVING STEPWISE/SMOOTH FREQUENCY TRANSITION AND RELATED SIGNAL TRANSMISSION METHOD THEREOF 有权
    具有用于生成具有步进/平滑频率转换的时钟信号的时钟信号发生器的信号传输系统及其相关信号传输方法

    公开(公告)号：US20120063534A1

    公开(公告)日：2012-03-15

    申请号：US13109015

    申请日：2011-05-17

    Applicant: Yu-Wei Lin ,  Chih-Chien Hung ,  Tsang-Yi Wu

    Inventor： Yu-Wei Lin ,  Chih-Chien Hung ,  Tsang-Yi Wu

    IPC: H04L27/00 ,  H03L7/06 ,  H03L7/00

    CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0091

    Abstract: A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.

    Abstract translation: 信号传输系统包括第一时钟信号发生器和第二时钟信号发生器。 第一时钟信号发生器被配置为根据从发送信号导出的时钟信息产生第一时钟信号，其中响应于第二时钟信号的频率变化而发送的信号被改变，并且第一时钟信号发生器输入频率 如果第二时钟信号在第一时间段期间具有从第一频率到第二频率的频率转变，则为非锁定状态。 第二时钟信号发生器被配置为在比第一时间段长的第二时间段内产生具有从第一频率到第二频率的频率转变的第二时钟信号，使得第一时钟信号发生器保持在锁频状态 在第二时期。

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