公开(公告)号：US20120106259A1

公开(公告)日：2012-05-03

申请号：US12915310

申请日：2010-10-29

申请人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

发明人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10

摘要： A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation.

摘要翻译： 一种方法包括在相同的编程周期中对多个存储单元执行第一编程操作; 以及对所述多个存储单元执行验证操作以在所述多个存储器单元中找到故障存储器单元，其中在所述第一编程操作中所述故障存储单元未成功编程; 以及对所述故障存储器单元执行第二编程操作。 在第二个编程操作中，没有编程在第一个编程操作中成功编程的通过的存储单元。

公开(公告)号：US08391073B2

公开(公告)日：2013-03-05

申请号：US12915310

申请日：2010-10-29

申请人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

发明人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10

摘要： A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation.

摘要翻译： 一种方法包括在相同的编程周期中对多个存储单元执行第一编程操作; 以及对所述多个存储单元执行验证操作以在所述多个存储器单元中找到故障存储器单元，其中在所述第一编程操作中所述故障存储单元未成功编程; 以及对所述故障存储器单元执行第二编程操作。 在第二个编程操作中，没有编程在第一个编程操作中成功编程的通过的存储单元。

公开(公告)号：US20070155092A1

公开(公告)日：2007-07-05

申请号：US11319357

申请日：2005-12-29

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7881 ,  H01J9/025 ,  H01L27/0207 ,  H01L29/40114

摘要： A method for forming a tip is disclosed. A layer is formed overlying a substrate. A mask layer is formed overlying the layer. The mask is patterned to form a mask pattern comprising an inner portion and an outer portion, wherein the inner portion is surrounded by the outer portion. The layer uncovered by the mask pattern is treated to form a reaction mask, wherein at least one portion of the reaction mask connect to form a tip of the layer under the inner portion of the mask pattern.

摘要翻译： 公开了一种用于形成尖端的方法。 层叠在衬底上方。 形成覆盖层的掩模层。 将掩模图案化以形成包括内部部分和外部部分的掩模图案，其中内部部分被外部部分包围。 处理由掩模图案覆盖的层以形成反应掩模，其中反应掩模的至少一部分连接以在掩模图案的内部部分的下方形成该顶层。

公开(公告)号：US06842381B2

公开(公告)日：2005-01-11

申请号：US10725809

申请日：2003-12-02

申请人： Yue-Der Chih ,  Ching-Huang Wang ,  Cheng-Hsiung Kuo

发明人： Yue-Der Chih ,  Ching-Huang Wang ,  Cheng-Hsiung Kuo

IPC分类号： G11C8/02 ,  G11C16/04 ,  G11C16/30 ,  G11C29/50

CPC分类号： G11C29/12005 ,  G11C16/04 ,  G11C16/30 ,  G11C29/50

摘要： Voltage-dropping components are bypassed during testing of the erasing of a flash memory device thereby effectively lowering the applied erase voltage to the marginal level desired (VME). These voltage-dropping components may be a plurality of diode-connected NMOS transistors. If a plurality of diode-connected NMOS transistors are used, the voltage applied to the flash macro is reduced by m*Vt, where m is the number of bypassed diode connected NMOS transistors and Vt is the threshold voltage of the NMOS transistors. In normal operation, the voltage dropping components are placed in series with the charge pump, thereby returning the voltage applied to the flash macro to the normal level (VNE).

摘要翻译： 在测试闪速存储器件的擦除期间旁路掉电元件，从而有效地将所施加的擦除电压降低到期望的边际电平（VME）。 这些降压组件可以是多个二极管连接的NMOS晶体管。 如果使用多个二极管连接的NMOS晶体管，则施加到闪存宏的电压减小m * Vt，其中m是旁路二极管连接的NMOS晶体管的数量，Vt是NMOS晶体管的阈值电压。 在正常操作中，降压元件与电荷泵串联放置，从而将施加到闪光灯的电压返回到正常电平（VNE）。

公开(公告)号：US09576949B2

公开(公告)日：2017-02-21

申请号：US13604299

申请日：2012-09-05

申请人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H01L29/66 ,  H01L27/07 ,  H01L27/02 ,  H01L29/872 ,  H01L29/06 ,  H02M3/07

CPC分类号： H01L27/0727 ,  H01L27/0222 ,  H01L29/0619 ,  H01L29/872 ,  H02M3/07

摘要： A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.

摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）包括栅极，连接到栅极的第一源极/漏极区域和栅极相对于第一源极/漏极的第二源极/漏极区域 地区。 第一肖特基二极管包括连接到第一源极/漏极区域的第一阳极和连接到PMOSFET主体的第一阴极。 第二肖特基二极管包括连接到第二源极/漏极区的第二阳极和连接到PMOSFET的主体的第二阴极。

公开(公告)号：US08610220B2

公开(公告)日：2013-12-17

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20140094009A1

公开(公告)日：2014-04-03

申请号：US14106100

申请日：2013-12-13

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20080024164A1

公开(公告)日：2008-01-31

申请号：US11496254

申请日：2006-07-31

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1778

摘要： A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).

摘要翻译： 公开了一种用于构造可重构可编程逻辑器件（PLD）的系统，该可重构可编程逻辑器件（PLD）包括具有第一源极，第一漏极和耦合到第一输入节点的第一栅极的第一P沟道非易失性存储器单元，第二P沟道非易失性存储单元 具有第二源极，耦合到第二输入节点的第二漏极和第二栅极，以及具有第三源极和第三漏极的NMOS晶体管，其中所述第一和第二源极共同连接到正电压源（Vcc） 第一，第二和第三漏极通常连接到输出节点，并且第三源耦合到互补的低电压源（Vss）。

公开(公告)号：US20140062580A1

公开(公告)日：2014-03-06

申请号：US13604299

申请日：2012-09-05

申请人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： G05F3/02

CPC分类号： H01L27/0727 ,  H01L27/0222 ,  H01L29/0619 ,  H01L29/872 ,  H02M3/07

摘要： A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.

摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）包括栅极，连接到栅极的第一源极/漏极区域和栅极相对于第一源极/漏极的第二源极/漏极区域 地区。 第一肖特基二极管包括连接到第一源极/漏极区域的第一阳极和连接到PMOSFET主体的第一阴极。 第二肖特基二极管包括连接到第二源极/漏极区的第二阳极和连接到PMOSFET的主体的第二阴极。

公开(公告)号：US08629706B2

公开(公告)日：2014-01-14

申请号：US13272584

申请日：2011-10-13

申请人： Hsu-Shun Chen ,  Cheng-Hsiung Kuo ,  Gu-Huan Li ,  Yue-Der Chih

发明人： Hsu-Shun Chen ,  Cheng-Hsiung Kuo ,  Gu-Huan Li ,  Yue-Der Chih

IPC分类号： H03L5/00

CPC分类号： H03K17/063 ,  H03K17/102

摘要： A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level.

摘要翻译： 电源开关包括控制电路，交叉耦合放大器，耦合在第一输出端子和第一受控接地端子之间的第一开关电路，以及耦合在第二输出端子和第二受控接地端子之间的第二开关电路。 控制电路被配置为在第一时间段期间将第二受控接地端子连接到地，使得第一输出端子处的电压电平从地面切换到第一电压电平，并将第二受控接地端子设置在升高的地面 在第二时段期间，第一输出端子处的电压电平保持在第一电压电平。