公开(公告)号：US06400257B1

公开(公告)日：2002-06-04

申请号：US09625885

申请日：2000-07-26

申请人： Yuen H. Chan ,  Anuj Kohli ,  John R. Rawlins

发明人： Yuen H. Chan ,  Anuj Kohli ,  John R. Rawlins

IPC分类号： G05B100

CPC分类号： H03K19/215 ,  G06F7/02 ,  H03K19/0948

摘要： A high performance CMOS comparator circuit is integrated with a bypass function allowing comparing first and second data sets (A & B) with a high data width (more than 30 and illustrated as 48 bits). In many cases, it is often required to compare not only sets A&B but also set A with an additional bypass set, and the preferred circuit embodiment permits this to be achieved.

摘要翻译： 高性能CMOS比较器电路集成了旁路功能，允许比较具有高数据宽度（大于30并被显示为48位）的第一和第二数据组（A和B）。 在许多情况下，通常需要比较不仅A和B组，而且还将A设置为附加旁路组，并且优选的电路实施例可以实现这一点。

公开(公告)号：US08963590B2

公开(公告)日：2015-02-24

申请号：US12424446

申请日：2009-04-15

申请人： Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

发明人： Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

IPC分类号： H03L7/00 ,  H03K3/02 ,  H03K17/04 ,  H03K17/22

CPC分类号： H03K17/223

摘要： A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.

摘要翻译： 提出了一种用于初始化电路的系统。 该系统采用具有阈值电压和可编程开关电路的上电复位电路。 上电复位电路具有用于检测参考电压的检测器电路和用于产生反映参考电压的输出电压的单侧锁存器。 检测器电路具有阈值，之后单侧锁存器被激活。 可编程开关电路接收上电复位电路的输出电压，并根据内部保险丝的状态产生使能信号及其补码。 上电复位电路的开关点提供输出电压的快速增加，以抵消可编程开关电路中的寄生漏电流，这可能导致不正确的使能信号输出。 在电源复位电路的输出节点上的高电阻直接接地路径可防止剩余电荷引起不期望的失火。

公开(公告)号：US20130250662A1

公开(公告)日：2013-09-26

申请号：US13429692

申请日：2012-03-26

申请人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

发明人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC分类号： G11C11/16 ,  H01L21/8246

CPC分类号： H01L23/57 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L23/573 ,  H01L27/228 ,  H01L43/02 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

摘要： A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.

摘要翻译： 磁阻随机存取存储器（MRAM）管芯可以包括MRAM单元，由MRAM管芯限定的储存器和设置在贮存器中的化学物质。 储存器的至少一个边界可以被配置为响应于试图篡改MRAM管芯而被损坏，使得当储存器的至少一个边界被损坏时，至少一些化学物质从贮存器释放。 在一些实例中，当化学品从储存器中释放时，至少一些化学物质被配置为接触和改变或损坏MRAM单元的至少一部分。

公开(公告)号：US20130241014A1

公开(公告)日：2013-09-19

申请号：US13419109

申请日：2012-03-13

申请人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

发明人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L23/57 ,  G06F21/86 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1695 ,  H01L23/573 ,  H01L27/222 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

摘要： A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.

摘要翻译： 磁阻随机存取存储器（MRAM）封装可以包括MRAM裸片，限定空腔和外表面的封装以及设置在封装体的腔体内或外表面上的磁性安全结构。 MRAM管芯可以设置在封装的空腔中，并且磁性安全结构可以包括至少三层，包括永磁层和软磁性层。

公开(公告)号：US20080309384A1

公开(公告)日：2008-12-18

申请号：US11762317

申请日：2007-06-13

申请人： Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

发明人： Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

IPC分类号： H03L7/00

CPC分类号： H03K17/223 ,  G06F1/24

摘要： A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output.

摘要翻译： 提出了一种用于初始化电路的系统。 该系统采用具有阈值电压和可编程开关电路的上电复位电路。 上电复位电路具有用于检测参考电压的检测器电路和用于产生反映参考电压的输出电压的单侧锁存器。 检测器电路具有阈值，之后单侧锁存器被激活。 可编程开关电路接收上电复位电路的输出电压，并根据内部保险丝的状态产生使能信号和补码。 上电复位电路的开关点提供输出电压的快速增加，抵消可编程开关电路中的寄生漏电流，从而导致不正确的使能信号输出。

公开(公告)号：US09042164B2

公开(公告)日：2015-05-26

申请号：US13429761

申请日：2012-03-26

申请人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

发明人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC分类号： G11C11/00 ,  H01L23/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L23/576 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

摘要： A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.

摘要翻译： 系统可以包括电路和包括至少一个MRAM单元的磁阻随机存取存储器（MRAM）管芯。 电路可以被配置为检测对MRAM管芯的尝试篡改，并且基于检测到的尝试篡改产生信号。 所述信号可能足以损坏或破坏所述至少一个MRAM单元的至少一层或电连接到所述至少一个MRAM单元的读取线的保险丝。

公开(公告)号：US08730715B2

公开(公告)日：2014-05-20

申请号：US13429692

申请日：2012-03-26

申请人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

发明人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC分类号： G11C11/00 ,  H01L23/00 ,  H01L23/02 ,  G11C11/16

CPC分类号： H01L23/57 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L23/573 ,  H01L27/228 ,  H01L43/02 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

摘要： A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.

摘要翻译： 磁阻随机存取存储器（MRAM）管芯可以包括MRAM单元，由MRAM管芯限定的储存器和设置在贮存器中的化学物质。 储存器的至少一个边界可以被配置为响应于试图篡改MRAM管芯而被损坏，使得当储存器的至少一个边界被损坏时，至少一些化学物质从贮存器释放。 在一些实例中，当化学品从储存器中释放时，至少一些化学物质被配置为接触和改变或损坏MRAM单元的至少一部分。

公开(公告)号：US20130250663A1

公开(公告)日：2013-09-26

申请号：US13429761

申请日：2012-03-26

申请人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

发明人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC分类号： G11C11/16

CPC分类号： H01L23/576 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

摘要： A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.

摘要翻译： 系统可以包括电路和包括至少一个MRAM单元的磁阻随机存取存储器（MRAM）管芯。 电路可以被配置为检测对MRAM管芯的尝试篡改，并且基于检测到的尝试篡改产生信号。 所述信号可能足以损坏或破坏所述至少一个MRAM单元的至少一层或电连接到所述至少一个MRAM单元的读取线的保险丝。

公开(公告)号：US20080054360A1

公开(公告)日：2008-03-06

申请号：US11469803

申请日：2006-09-01

申请人： Harry HL Liu ,  Anuj Kohli ,  Michael S. Liu

发明人： Harry HL Liu ,  Anuj Kohli ,  Michael S. Liu

IPC分类号： H01L27/12

CPC分类号： H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.

摘要翻译： 描述了用于调节光电流的方法和装置。 光电流调节器可以包括具有相关横截面积的晶体管。 光电流调节器耦合在集成电路和电压源之间。 当在集成电路内发生剂量率事件时，光电流调节器通过横截面积调节到电压源的复合路径。 因此，集成电路内的光电流被调节，防止集成电路内的永久性损坏。

公开(公告)号：US08854870B2

公开(公告)日：2014-10-07

申请号：US13419066

申请日：2012-03-13

申请人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

发明人： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC分类号： G11C11/00

CPC分类号： H01L23/573 ,  G06F21/79 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L27/226 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer.

摘要翻译： MRAM管芯可以包括第一写入线，第二写入线，布置在第一写入线和第二写入线之间的MRAM单元，以及与MRAM单元相邻的磁性安全结构。 磁性安全结构可以包括永久磁性层和软磁性层。