公开(公告)号：US07888139B2

公开(公告)日：2011-02-15

申请号：US12549261

申请日：2009-08-27

申请人： Yukiteru Matsui ,  Takeo Kubota ,  Yoshikuni Tateyama ,  Hiroyuki Kanaya ,  Yoshihiro Minami

发明人： Yukiteru Matsui ,  Takeo Kubota ,  Yoshikuni Tateyama ,  Hiroyuki Kanaya ,  Yoshihiro Minami

IPC分类号： H01L21/00

CPC分类号： H01L27/11507 ,  H01L21/0206 ,  H01L21/31053 ,  H01L21/32139 ,  H01L28/55

摘要： A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

摘要翻译： 第一电极膜，铁电体膜和第二电极膜依次堆积在半导体上方，硬掩模在第二电极上方积聚，用表面活性剂对硬掩模的表面进行擦洗清洗 根据铁电电容器的平面形状，对其进行擦洗清洁的掩模进行了图案化，并且通过使用已经被图案化的硬掩模作为硬掩模来进行蚀刻。

公开(公告)号：US20100144062A1

公开(公告)日：2010-06-10

申请号：US12549261

申请日：2009-08-27

申请人： Yukiteru MATSUI ,  Takeo Kubota ,  Yoshikuni Tateyama ,  Hiroyuki Kanaya ,  Yoshihiro Minami

发明人： Yukiteru MATSUI ,  Takeo Kubota ,  Yoshikuni Tateyama ,  Hiroyuki Kanaya ,  Yoshihiro Minami

IPC分类号： H01L21/8246

CPC分类号： H01L27/11507 ,  H01L21/0206 ,  H01L21/31053 ,  H01L21/32139 ,  H01L28/55

摘要： A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

摘要翻译： 第一电极膜，铁电体膜和第二电极膜依次堆积在半导体上方，硬掩模在第二电极上方积聚，用表面活性剂对硬掩模的表面进行擦洗清洗 根据铁电电容器的平面形状，对其进行擦洗清洁的掩模进行了图案化，并且通过使用已经被图案化的硬掩模作为硬掩模来进行蚀刻。

公开(公告)号：US09171886B2

公开(公告)日：2015-10-27

申请号：US13032359

申请日：2011-02-22

申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

IPC分类号： H01L29/82 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上提供布线。

公开(公告)号：US08786038B2

公开(公告)日：2014-07-22

申请号：US13230746

申请日：2011-09-12

申请人： Keiji Hosotani ,  Hiroyuki Kanaya

发明人： Keiji Hosotani ,  Hiroyuki Kanaya

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.

摘要翻译： 根据本实施例的半导体存储装置包括形成在半导体衬底的表面上的选择元件。 下电极连接到选择元件。 在下电极上设置磁性隧道结元件。 上部电极设置在磁性隧道结元件上。 生长层设置在上电极上并由导电材料构成，并且当从半导体衬底的表面上方观察时具有比上电极大的面积。 在生长层上设置布线。

公开(公告)号：US20110266600A1

公开(公告)日：2011-11-03

申请号：US13032359

申请日：2011-02-22

申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上设置接线。

公开(公告)号：US07750383B2

公开(公告)日：2010-07-06

申请号：US11858361

申请日：2007-09-20

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L27/108

CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/56

摘要： According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the insulating film, a ferroelectric film disposed on the lower electrode and an upper electrode disposed on the ferroelectric film. The upper mask includes a hard mask disposed on the upper electrode and a sidewall mask disposed on at least part of a sidewall of the hard mask.

摘要翻译： 根据本发明的一个方面，提供一种包括半导体衬底，形成在半导体衬底上的晶体管，设置在半导体衬底上的绝缘膜，铁电电容器和上掩模的半导体器件。 铁电电容器包括设置在绝缘膜上的下电极，设置在下电极上的铁电体膜和设置在铁电体膜上的上电极。 上掩模包括设置在上电极上的硬掩模和设置在硬掩模的侧壁的至少一部分上的侧壁掩模。

公开(公告)号：US07700987B2

公开(公告)日：2010-04-20

申请号：US11276781

申请日：2006-03-14

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L27/108

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

摘要： A ferroelectric memory device includes a top electrode, a bottom electrode, a ferroelectric film which is sandwiched between the top and bottom electrodes, includes a first portion having a side surface flushed with a side surface of the top electrode and a second portion having a side surface flushed with a side surface of the bottom electrode, and has a step formed by making the side surface of the second portion project outward from the side surface of the first portion, a top mask which is provided on the top electrode, and a side mask which is provided on part of a side surface of the top mask, the side surfaces of the top electrode and the first portion of the ferroelectric film and has a top at a lower level than a top of the top mask and at a higher level than a top of the top electrode.

摘要翻译： 铁电存储器件包括顶电极，底电极，夹在顶电极和底电极之间的铁电膜，包括具有用顶电极的侧表面冲洗的侧表面的第一部分和具有侧面的第二部分 表面用底部电极的侧表面冲洗，并且具有通过使第二部分的侧表面从第一部分的侧表面向外突出，设置在顶部电极上的顶部掩模和侧面 掩模，其设置在顶部掩模的侧表面的一部分，顶部电极的侧表面和铁电体膜的第一部分上，并且具有比顶部掩模的顶部更低的顶部和更高的水平面 比顶部电极的顶部。

公开(公告)号：US07531408B2

公开(公告)日：2009-05-12

申请号：US11754022

申请日：2007-05-25

申请人： Keisuke Nakazawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Soichi Yamazaki ,  Hiroshi Itokawa ,  Hiroyuki Kanaya

发明人： Keisuke Nakazawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Soichi Yamazaki ,  Hiroshi Itokawa ,  Hiroyuki Kanaya

IPC分类号： H01L21/8234

CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

摘要： A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.

摘要翻译： 一种半导体器件的制造方法，包括在半导体衬底上形成电容器，所述电容器包括含有Pb，Zr，Ti和O的电介质膜。形成所述电容器包括形成含有Pb，Sr，Zr，Ti， 汝和O.

公开(公告)号：US20090095994A1

公开(公告)日：2009-04-16

申请号：US12250888

申请日：2008-10-14

申请人： Hiroyuki Kanaya ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Yoshinori Kumura

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/44

CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/65

摘要： A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.

摘要翻译： 半导体器件包括衬底; 形成在所述基板上的绝缘层; 穿过所述绝缘层形成的接触孔; 多个第一插头电极，每个第一插头电极各自形成在所述接触孔内部到所述绝缘层的表面; 在第一区域中形成在所述第一插头电极上的电容器层; 以及形成在与第一区域不同的第二区域中的第一插塞电极上的第二插头电极。 电容器层包括下电极，铁电体膜和依次堆叠的上电极。 第一插头电极包括从基板的表面形成的插头导电层和从插塞导电层的上方形成的插塞阻挡层，直到绝缘层的上表面，插塞阻挡层具有比 下电极。

公开(公告)号：US07045837B2

公开(公告)日：2006-05-16

申请号：US10356314

申请日：2003-01-31

申请人： Ulrich Egger ,  Haoren Zhuang ,  Yoshinoru Kumura ,  Kazuhiro Tomioka ,  Hiroyuki Kanaya

发明人： Ulrich Egger ,  Haoren Zhuang ,  Yoshinoru Kumura ,  Kazuhiro Tomioka ,  Hiroyuki Kanaya

IPC分类号： H01L29/76

CPC分类号： H01L28/65 ,  H01L21/32136 ,  H01L21/32139 ,  H01L28/55

摘要： The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.

摘要翻译： 本发明通过使用相对于下层阻挡层具有高蚀刻选择性的硬掩模来提供相对不含栅栏的铁电体元件。 本发明还包括一种用于抑制附着在铁电体器件的侧壁上的栅栏的方法。 此外，与现有技术的装置相比，本发明提供一种具有与下层阻挡层相比较薄的硬掩模的铁电体装置。