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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20080251838A1

    公开(公告)日：2008-10-16

    申请号：US12118159

    申请日：2008-05-09

    申请人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

    发明人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7809

    摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.

    摘要翻译： 半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上， 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

    Vertical-type power MOSFET with a gate formed in a trench
    3.
    发明授权
    Vertical-type power MOSFET with a gate formed in a trench 有权
    垂直型功率MOSFET，其栅极形成在沟槽中

    公开(公告)号：US06878992B2

    公开(公告)日：2005-04-12

    申请号：US10091423

    申请日：2002-03-07

    申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Kazutoshi Nakamura ,  Akio Nakagawa ,  Syotaro Ono

    发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Kazutoshi Nakamura ,  Akio Nakagawa ,  Syotaro Ono

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/66666 ,  H01L29/42368 ,  H01L29/7828

    摘要： A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.

    摘要翻译： 功率MOSFET在源极和漏极之间包括第一导电类型的低电阻半导体衬底，形成在半导体衬底上的第一导电类型的漂移层，形成在漂移上的第一导电类型的高电阻外延层 形成为从外延层的表面延伸到漂移层中的沟槽，埋入沟槽中的栅电极，栅极绝缘膜插入在栅电极和沟槽的壁之间，形成在第一导电类型的低电阻源层 与栅极绝缘膜相邻的外延层的表面区域和形成在外延层的表面区域中的第二导电类型的基极层，其中在0伏特的情况下，介于沟槽之间的外延层被耗尽 施加在源电极和栅电极之间。

    Power MOSFET device
    8.
    发明授权
    Power MOSFET device 有权
    功率MOSFET器件

    公开(公告)号：US06720618B2

    公开(公告)日：2004-04-13

    申请号：US10055947

    申请日：2002-01-28

    申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

    发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

    IPC分类号： H01L2976

    CPC分类号： H01L21/26513 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41 ,  H01L29/4175 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7835

    摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

    摘要翻译： 一种功率MOSFET器件，包括第一导电类型的低电阻衬底，形成在低电阻衬底上的第一导电类型的高电阻外延层，形成在高电阻外延表面区域中的第二导电类型的基极层 形成在基底层的表面区域中的第一导电类型的源极区域，形成在基极层的表面上以与源极区域接触的栅极绝缘膜，形成在栅极绝缘膜上的栅电极， 以及形成在所述高电阻外延层的与所述源极区域和所述栅极电极相反的表面上的所述第一导电类型的LDD层，其中所述LDD层和所述低电阻衬底通过所述高电阻外延层彼此连接 。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06977414B2

    公开(公告)日：2005-12-20

    申请号：US10460407

    申请日：2003-06-13

    申请人： Kazutoshi Nakamura ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Syotaro Ono ,  Akio Nakagawa

    发明人： Kazutoshi Nakamura ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Syotaro Ono ,  Akio Nakagawa

    IPC分类号： H01L21/285 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L29/7816 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4238 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7809

    摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a pair of base regions of a second conductivity type selectively provided on a surface of the semiconductor layer; and source regions of a first conductivity type, each of the source regions being selectively provided on a surface of each of the base regions. The semiconductor device further comprises an electrical field reducing region of a second conductivity type selectively provided on the surface of the semiconductor layer between the pair of the base regions; a gate insulating film provided on the surface of the base regions; a pair of gate electrodes provided on the gate insulating film, each of the gate electrodes being provided on the surface of the base regions between the source region and the electrical field reducing region; and a source electrode connected to the source regions. The electrical field reducing region is isolated from both of the gate electrode and the source electrode.

    摘要翻译： 半导体器件包括：第一导电类型的半导体层; 选择性地设置在半导体层的表面上的一对第二导电类型的基极区; 以及第一导电类型的源极区域，每个源区域选择性地设置在每个基极区域的表面上。 所述半导体器件还包括选择性地设置在所述一对基极区域之间的所述半导体层的表面上的第二导电类型的电场减小区域; 设置在所述基底区域的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的一对栅电极，在所述源极区域和所述电场减少区域之间的所述基极区域的表面上设置各栅极电极; 以及与源极区域连接的源电极。 电场减少区域与栅极电极和源极电极隔离。