公开(公告)号：US06967873B2

公开(公告)日：2005-11-22

申请号：US10677790

申请日：2003-10-02

申请人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

发明人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0475 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

公开(公告)号：US06795342B1

公开(公告)日：2004-09-21

申请号：US10307667

申请日：2002-12-02

申请人： Yi He ,  Zhizheng Liu ,  Mark W. Randolph ,  Sameer S. Haddad

发明人： Yi He ,  Zhizheng Liu ,  Mark W. Randolph ,  Sameer S. Haddad

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C16/0475 ,  G11C16/0491

摘要： A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.

摘要翻译： 一种用于对存储在双位介质存储器单元阵列内的第一双位介质存储单元的介电电荷俘获层的电荷存储区域上的电荷进行编程的系统包括将正源编程偏置施加到第一位线 同时将漏极编程电压施加到与沟道区形成漏极结的第二位线以及向所选择的字线施加正电压的所选存储单元的源极。 可以通过将源极线耦合到分压器或通过将源极线耦合到电阻器来施加源极电压，电阻器又连接到地电位器。 负编程偏置也可以应用于衬底和未选择的字线。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US06795357B1

公开(公告)日：2004-09-21

申请号：US10283590

申请日：2002-10-30

申请人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

发明人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

IPC分类号： G11C700

CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/26

摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.

摘要翻译： 检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加 到与沟道区形成漏极结的第二位线的漏极电压。 源极电压可以是小的正电压，并且漏极电压可能大于源极电压。 将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。 偏置电压可以是负电压。

公开(公告)号：US06788583B2

公开(公告)日：2004-09-07

申请号：US10307749

申请日：2002-12-02

申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

IPC分类号： G11C1606

CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

公开(公告)号：US06906959B2

公开(公告)日：2005-06-14

申请号：US10306252

申请日：2002-11-27

申请人： Mark W. Randolph ,  Chi Chang ,  Yi He ,  Wei Zheng ,  Edward F. Runnion ,  Zhizheng Liu

发明人： Mark W. Randolph ,  Chi Chang ,  Yi He ,  Wei Zheng ,  Edward F. Runnion ,  Zhizheng Liu

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/14 ,  H01L29/7923

摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.

摘要翻译： 本发明是一种擦除氮化物存储器件的方法和系统。 在本发明的一个实施例中，在半导体衬底中形成隔离的P阱。 在分离的P阱中形成多个N型杂质浓度，并且在两种N型杂质浓度之间制造氮化物存储单元。 最后，电接点耦合到隔离的P阱。

公开(公告)号：US06639844B1

公开(公告)日：2003-10-28

申请号：US10099499

申请日：2002-03-13

申请人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph

发明人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3404 ,  G11C16/344

摘要： A method for correcting overerasure in a multi-bit memory device. A sector of multi-bite memory cells in the device is erased and verified. After erase and verification, the overerased memory cells are soft programmed and verified to correct for overerasure. A soft programming pulse with a Vg to Vd ratio (Vg/Vd) greater than or equal to two is used.

摘要翻译： 一种用于在多位存储器件中校正过度曝光的方法。 器件中的多点存储器单元的扇区被擦除和验证。 在擦除和验证之后，过高的存储单元被软编程并被验证以校正过高。 使用Vg至Vd比（Vg / Vd）大于或等于2的软编程脉冲。

公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US06897110B1

公开(公告)日：2005-05-24

申请号：US10305750

申请日：2002-11-26

申请人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

发明人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.

摘要翻译： 一种制造存储器阵列的方法，同时保护其免受电荷损坏。 可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。 字线形成在位线之上，并且可以具有栅极区域。 接下来，在位线之上形成耦合到位线之一的第一金属区域。 形成不与第一金属区电耦合的第二金属区域。 然后，第一金属区域电耦合到第二金属区域。 通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。 为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。 此外，可以在位线和字线之间形成保险丝，以保护字线。

公开(公告)号：US07573103B1

公开(公告)日：2009-08-11

申请号：US11855704

申请日：2007-09-14

申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

IPC分类号： H01L27/06

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.

摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底 线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到 存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域 金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底 线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到 存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱 金属线。