公开(公告)号：US20110116067A1

公开(公告)日：2011-05-19

申请号：US13003294

申请日：2009-07-07

申请人： Jun Ye ,  Yu Cao ,  Hanying Feng

发明人： Jun Ye ,  Yu Cao ,  Hanying Feng

IPC分类号： G03B27/54

CPC分类号： G03F7/70441 ,  G03F7/70091 ,  G03F7/70666

摘要： A method of optimizing an illumination pupil shape for a lithographic process 1 comprises identifying a target pattern (206) to be imaged by said lithographic process. It further comprises identifying at least one optimization point (262) in said target pattern and identifying at least one design for manufacturing metric (270) per optimization point. Additionally it comprises selecting a set of illumination source points (274) based on the identified at least one design for manufacturing metric and determining the illumination pupil shape (284) based on the selected set of illumination source points.

摘要翻译： 优化用于光刻工艺1的照明光瞳形状的方法包括识别通过所述光刻工艺成像的目标图案（206）。 它还包括识别所述目标图案中的至少一个优化点（262），并且识别用于每个优化点的制造度量（270）的至少一个设计。 另外，它包括基于所识别的用于制造度量的所述至少一个设计来选择一组照明源点（274），并且基于所选择的一组照明源点确定照明光瞳形状（284）。

公开(公告)号：US07558419B1

公开(公告)日：2009-07-07

申请号：US10917060

申请日：2004-08-12

申请人： Jun Ye ,  Yu Cao ,  R. Fabian Pease

发明人： Jun Ye ,  Yu Cao ,  R. Fabian Pease

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G03F1/84 ,  G06T2207/30148

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for inspecting integrated circuits, including, for example, patterns projected, provided or formed on a wafer using photomasks, or patterns on the photomask itself. The inspection system and technique of this aspect includes first identifying, determining and/or detecting areas and/or patterns that are potentially defective by removing, filtering and/or eliminating from a set of potential defects any and/or all typical, regular or normal patterns. The identification, determination and/or detection of potential defects may be performed relatively quickly by a rapidly executing algorithm. In this way, a first or “coarse” analysis is performed rapidly and some, many, all or substantially all of the regular, normal or typical patterns are eliminated from further analysis. Thereafter, a second more detailed analysis is performed. This second analysis focuses on the set of potential defects that were identified, determined and/or detected during the first analysis of the photomask or wafer (i.e., the “coarse” analysis). The second analysis may be considerably a more detailed or a “fine” analysis relative to the first or “coarse” analysis. Indeed, in one embodiment, the second analysis may implement a more computational intensive process, without sacrificing throughput, since only a small portion of the photomask or wafer is inspected in the second analysis. In this way, the detailed analysis of the defect candidates may identify (i) all or substantially all of the actual defects and/or (ii) only the actual defects from the potential defects identified during the first analysis.

摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于检查集成电路的技术和系统，包括例如使用光掩模投影，提供或形成在晶片上的图案或光掩模本身上的图案。 该方面的检查系统和技术包括首先识别，确定和/或检测潜在缺陷的区域和/或图案，该区域和/或图案通过去除，过滤和/或从一组潜在的缺陷中消除任何和/或所有典型的，规则的或正常的 模式。 可能通过快速执行的算法相对较快地执行潜在缺陷的识别，确定和/或检测。 以这种方式，快速执行第一个或“粗略”分析，并从进一步的分析中消除一些，许多，全部或基本上所有常规，正常或典型的模式。 此后，进行第二更详细的分析。 该第二分析集中在在光掩模或晶片的第一次分析期间（即，“粗略”分析））中识别，确定和/或检测到的潜在缺陷集合。 第二次分析可能相对于第一次或“粗略”分析可能是更详细或“精细”的分析。 实际上，在一个实施例中，第二分析可以实现更加计算密集的过程，而不会牺牲吞吐量，因为在第二次分析中只检查了一小部分光掩模或晶片。 以这种方式，缺陷候选人的详细分析可以识别（i）所有或基本上所有的实际缺陷和/或（ii）仅在第一次分析期间识别的潜在缺陷的实际缺陷。

公开(公告)号：US20070061772A1

公开(公告)日：2007-03-15

申请号：US11530402

申请日：2006-09-08

申请人： Jun Ye ,  Stefan Hunsche

发明人： Jun Ye ,  Stefan Hunsche

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/84 ,  G03F7/70441 ,  G03F7/705

摘要： Methods and systems are disclosed to inspect a manufactured lithographic mask, to extract physical mask data from mask inspection data, to determine systematic mask error data based on differences between the physical mask data and mask layout data, to generate systematic mask error parameters based on the systematic mask error data, to create an individual mask error model with systematic mask error parameters, to predict patterning performance of the lithographic process using a particular mask and/or a particular projection system, and to predict process corrections that optimize patterning performance and thus the final device yield.

摘要翻译： 公开了用于检查制造的光刻掩模的方法和系统，以从掩模检查数据提取物理掩模数据，以基于物理掩模数据和掩模布局数据之间的差异来确定系统掩模误差数据，以基于 系统掩模误差数据，以产生具有系统掩模误差参数的单独掩模误差模型，以预测使用特定掩模和/或特定投影系统的光刻工艺的图案化性能，以及预测优化图案化性能的工艺校正， 最终装置产量。

公开(公告)号：US07120895B2

公开(公告)日：2006-10-10

申请号：US11084484

申请日：2005-03-18

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US07114145B2

公开(公告)日：2006-09-26

申请号：US10989972

申请日：2004-11-16

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US06969837B2

公开(公告)日：2005-11-29

申请号：US10863915

申请日：2004-06-09

申请人： Jun Ye ,  R. Fabian W. Pease ,  Xun Chen

发明人： Jun Ye ,  R. Fabian W. Pease ,  Xun Chen

IPC分类号： G01N21/956 ,  G01J1/02 ,  G01J1/04 ,  G01M11/00 ,  G03F1/08 ,  G03F7/20 ,  H01L21/027 ,  H01L27/14 ,  H01L27/00

CPC分类号： G03F7/7085 ,  G03F7/70591 ,  G03F7/7065

摘要： A system and sensor for measuring, inspecting, characterizing, evaluating and/or controlling optical lithographic equipment and/or materials used therewith, for example, photomasks. In one embodiment, the system and sensor measures, collects and/or detects an aerial image (or portion thereof) produced or generated by the interaction between the photomask and lithographic equipment. An image sensor unit may measure, collect, sense and/or detect the aerial image in situ—that is, the aerial image at the wafer plane produced, in part, by a production-type photomask (i.e., a wafer having integrated circuits formed therein/thereon) and/or by associated lithographic equipment used, or to be used, to manufacture of integrated circuits. A processing unit, coupled to the image sensor unit, may generate image data which is representative of the aerial image by interleaving the intensity of light sampled by each sensor cell at the plurality of location of the platform.

摘要翻译： 用于测量，检查，表征，评估和/或控制与其一起使用的光学平版印刷设备和/或材料的系统和传感器，例如光掩模。 在一个实施例中，系统和传感器测量，收集和/或检测由光掩模和光刻设备之间的相互作用产生或产生的空间图像（或其部分）。 图像传感器单元可以原位测量，收集，感测和/或检测空中图像，即在晶片平面上的部分由生产型光掩模（即，形成有集成电路的晶片）产生的空间图像 其中/之上）和/或通过使用或用于制造集成电路的相关平版印刷设备。 耦合到图像传感器单元的处理单元可以通过交织由平台的多个位置处的每个传感器单元采样的光的强度来生成代表空间图像的图像数据。

公开(公告)号：US07587704B2

公开(公告)日：2009-09-08

申请号：US11530402

申请日：2006-09-08

申请人： Jun Ye ,  Stefan Hunsche

发明人： Jun Ye ,  Stefan Hunsche

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/84 ,  G03F7/70441 ,  G03F7/705

摘要： Methods and systems are disclosed to inspect a manufactured lithographic mask, to extract physical mask data from mask inspection data, to determine systematic mask error data based on differences between the physical mask data and mask layout data, to generate systematic mask error parameters based on the systematic mask error data, to create an individual mask error model with systematic mask error parameters, to predict patterning performance of the lithographic process using a particular mask and/or a particular projection system, and to predict process corrections that optimize patterning performance and thus the final device yield.

摘要翻译： 公开了用于检查制造的光刻掩模的方法和系统，以从掩模检查数据提取物理掩模数据，以基于物理掩模数据和掩模布局数据之间的差异来确定系统掩模误差数据，以基于 系统掩模误差数据，以产生具有系统掩模误差参数的单独掩模误差模型，以预测使用特定掩模和/或特定投影系统的光刻工艺的图案化性能，以及预测优化图案化性能的工艺校正， 最终装置产量。

公开(公告)号：US07488933B2

公开(公告)日：2009-02-10

申请号：US11461929

申请日：2006-08-02

申请人： Jun Ye ,  Yu Cao ,  Guangqing Chen ,  Stefan Hunsche

发明人： Jun Ye ,  Yu Cao ,  Guangqing Chen ,  Stefan Hunsche

IPC分类号： G12B13/00

CPC分类号： G03F7/70516 ,  G03F7/705

摘要： A method for separately calibrating an optical model and a resist model of lithography process using information derived from in-situ aerial image measurements to improve the calibration of both the optical model and the resist model components of the lithography simulation model. Aerial images produced by an exposure tool are measured using an image sensor array loaded into the exposure tool. Multiple embodiments of measuring aerial image information and using the measured aerial image information to calibrate the optical model and the resist model are disclosed. The method of the invention creates more accurate and separable optical and resist models, leading to better predictability of the pattern transfer process from mask to wafer, more accurate verification of circuit patterns and how they will actually print in production, and more accurate model-based process control in the wafer fabrication facility.

摘要翻译： 使用从原位空间图像测量得到的信息分别校准光学模型和光刻工艺的抗蚀剂模型的方法，以改进光刻模拟和光刻模拟模型的抗蚀剂模型组件的校准。 使用装载到曝光工具中的图像传感器阵列来测量由曝光工具产生的空中影像。 公开了测量空间图像信息和使用所测量的空间图像信息来校准光学模型和抗蚀剂模型的多个实施例。 本发明的方法创建更精确和可分离的光学和抗蚀剂模型，导致从掩模到晶片的图案转移过程更好的可预测性，电路图案的更准确的验证以及它们将如何在生产中实际打印，以及更准确的基于模型 晶圆制造设备中的过程控制。

公开(公告)号：US20080301620A1

公开(公告)日：2008-12-04

申请号：US11757805

申请日：2007-06-04

申请人： Jun Ye ,  Yu Cao ,  Hanying Feng

发明人： Jun Ye ,  Yu Cao ,  Hanying Feng

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/36

摘要： Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine tune already-placed SRAFs. In another embodiment the SRAF guidance map is used directly to place SRAFs in a mask layout.

摘要翻译： 公开了创建有效的基于模型的子分辨率辅助特征（MB-SRAF）的方法。 创建SRAF指南图，其中每个设计目标边缘位置对于给定的场点投票，放置在该场点上的单像素SRAF是否将改善或降级过程窗口上的空中图像。 在一个实施例中，SRAF引导图用于确定SRAF放置规则和/或微调已经放置的SRAF。 在另一个实施例中，SRAF引导图被直接用于将SRAF放置在掩模布局中。

公开(公告)号：US07233874B2

公开(公告)日：2007-06-19

申请号：US11041807

申请日：2005-01-24

申请人： Jun Ye ,  Xun Chen

发明人： Jun Ye ,  Xun Chen

IPC分类号： G06F19/00

CPC分类号： H01L21/67276 ,  G01D9/005 ,  H01L21/67253 ,  H01L22/34 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

摘要： In one aspect, the present invention is a sensor unit for sensing process parameters of a process to manufacture an integrated circuit using integrated circuit processing equipment. In one embodiment, the sensor unit includes a substrate having a wafer-shaped profile and a first sensor, disposed on or in the substrate, to sample a first process parameter. The sensor unit of this embodiment also includes a second sensor, disposed on or in the substrate, to sample a second process parameter wherein the second process parameter is different from the first process parameter. In one embodiment, the sensor unit includes a first source, disposed on or in the substrate, wherein first source generates an interrogation signal and wherein the first sensor uses the interrogation signal from the first source to sample the first process parameter. The sensor unit may also include a second source, disposed on or in the substrate, wherein second source generates an interrogation signal and wherein the second sensor uses the interrogation signal from the second source to sample the second process parameter. The first sensor and the first source may operate in an end-point mode or in a real-time mode. In this regard, the first sensor samples the first parameter periodically or continuously while the sensor unit is disposed in the integrated circuit processing equipment and undergoing processing. In one embodiment, the first sensor is a temperature sensor and the second sensor is a pressure sensor, a chemical sensor, a surface tension sensor or a surface stress sensor.

摘要翻译： 一方面，本发明是用于感测使用集成电路处理设备来制造集成电路的工艺参数的传感器单元。 在一个实施例中，传感器单元包括具有晶片形状的衬底和设置在衬底上或衬底中的第一传感器，以对第一工艺参数进行采样。 该实施例的传感器单元还包括设置在基板上或基板中的第二传感器，以对第二处理参数进行采样，其中第二处理参数与第一处理参数不同。 在一个实施例中，传感器单元包括设置在衬底上或衬底中的第一源，其中第一源产生询问信号，并且其中第一传感器使用来自第一源的询问信号对第一过程参数进行采样。 传感器单元还可以包括设置在衬底上或衬底中的第二源，其中第二源产生询问信号，并且其中第二传感器使用来自第二源的询问信号对第二过程参数进行采样。 第一传感器和第一源可以以端点模式或实时模式工作。 在这方面，第一传感器在传感器单元被布置在集成电路处理设备中并进行处理时周期性地或连续地对第一参数进行采样。 在一个实施例中，第一传感器是温度传感器，第二传感器是压力传感器，化学传感器，表面张力传感器或表面应力传感器。