公开(公告)号：US20240333275A1

公开(公告)日：2024-10-03

申请号：US18194240

申请日：2023-03-31

申请人： GAN SYSTEMS INC.

发明人： Iman Abdali Mashhadi

IPC分类号： H03K17/0412 ,  H03K17/16

CPC分类号： H03K17/04123 ,  H03K17/162 ,  H03K2217/0081

摘要： A control driver circuit that includes a switching transistor coupled between a first voltage supply node and an output node of the gate, the output node coupled or couplable to a control node of the power transistor. A circuit includes an inductive element coupled between the control transistor and a second voltage supply node. The circuit is configured such that if the output node is coupled to the power transistor, and in response to the switching transistor being turned on, a current is induced within the inductive element and a voltage from the first voltage supply is provided to a control node of the power transistor to thereby turn on the power transistor. On the other hand, in response to the switching transistor being turned off, the induced current is drawn from the output node to thereby turn the power transistor off.

公开(公告)号：US12107416B2

公开(公告)日：2024-10-01

申请号：US17975092

申请日：2022-10-27

申请人： GaN Systems Inc.

发明人： Ahmad Mizan ,  Edward Macrobbie

IPC分类号： H02H9/00 ,  H01L27/02 ,  H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

摘要： A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

公开(公告)号：US20240313651A1

公开(公告)日：2024-09-19

申请号：US18185098

申请日：2023-03-16

申请人： GAN SYSTEMS INC.

发明人： Nan XING ,  Yinglai XIA ,  Yalong LI

IPC分类号： H02M3/158 ,  H02M1/00

CPC分类号： H02M3/158 ,  H02M1/0009

摘要： A power transistor current sense circuit. The control nodes of each of a power transistor and sense transistors are connected. The input nodes of the power transistor and each of the sense transistors are also connected. A voltage divider is connected between a reference voltage source and the output node of a second sense transistor. A negative feedback circuit is connected between the output of the voltage divider and the output node of the first sense transistor. The negative feedback circuit forces a voltage at the output node of the first sense transistor to be approximately equal to the divided voltage. A power transistor current determination component measures a sense current that passes through the first sense transistor, and from that detects the current passing through the power transistor.

公开(公告)号：US12040257B2

公开(公告)日：2024-07-16

申请号：US17974880

申请日：2022-10-27

申请人： GaN Systems Inc.

发明人： Ahmad Mizan ,  Edward Macrobbie

IPC分类号： H01L23/482 ,  H01L29/20 ,  H01L29/778

CPC分类号： H01L23/4824 ,  H01L29/2003 ,  H01L29/7786

摘要： Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

公开(公告)号：US20230402342A1

公开(公告)日：2023-12-14

申请号：US18094477

申请日：2023-01-09

申请人： GaN Systems Inc.

发明人： Di CHEN ,  Juncheng LU ,  Ahmad MIZAN ,  Ruoyu HOU ,  Abhinandan DIXIT

IPC分类号： H01L23/367 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L23/3672 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

摘要： Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers, and wherein a first thermal pad on one side of the package and a second thermal pad on an opposite side of the package provides for dual-side cooling. Example embodiments of the dual-side cooled package may be based on a bottom-side cooled layup with a primary bottom-side thermal pad and a secondary top-side thermal pad, or a top-side cooled layup with primary top-side thermal pad and a secondary bottom side thermal pad, using layups with or without a leadframe. For example, the power semiconductor switching device comprises a GaN power transistor, such as a GaN HEMT rated for operation at ≥100V or ≥600V, for switching tens or hundreds of Amps.

公开(公告)号：US11831303B2

公开(公告)日：2023-11-28

申请号：US17533365

申请日：2021-11-23

申请人： GaN Systems Inc.

发明人： Xuechao Liu ,  Ruoyu Hou

IPC分类号： H03K17/082 ,  H02M1/00 ,  H02M1/32 ,  H01L29/20 ,  H02M3/335 ,  H03K17/08

CPC分类号： H03K17/0822 ,  H01L29/2003 ,  H02M1/0009 ,  H02M1/32 ,  H02M3/33569 ,  H03K2017/0806 ,  H03K2217/0027

摘要： High accuracy current sense circuitry for power switching devices comprising GaN power transistors provides for current feedback functions, e.g. current loop control, over-current protection (OCP) and short-circuit protection (SCP). The current sense circuitry comprises a current mirror sense GaN transistor (Sense_GaN) and a power GaN transistor (Power_GaN) and a sampling circuit. The sampling circuit comprises first and second stage operational amplifiers to provide fast response and improved current sense accuracy, e.g. better than 1%, over a range of junction temperatures Tj. The Sense_GaN, Power_GaN and first stage operational amplifier have a common ground referenced to a Kelvin Source of the Power_GaN, so that the Sense_GaN and Power_GaN operate with the same gate-to-source voltage Vgs, to provide an accurate current ratio. Applications include current sensing for switching mode power supplies that need high speed and lossless current sense for current protection and feedback.

公开(公告)号：USRE49603E1

公开(公告)日：2023-08-08

申请号：US16868632

申请日：2020-05-07

申请人： GaN Systems Inc.

发明人： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC分类号： H01L21/304 ,  H01L27/088 ,  H01L29/20 ,  H01L23/528 ,  H01L23/31 ,  H01L23/58 ,  H01L21/02 ,  H01L29/778 ,  H01L21/78

CPC分类号： H01L27/088 ,  H01L21/3043 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/585 ,  H01L29/2003 ,  H01L29/778

摘要： A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US20230198252A1

公开(公告)日：2023-06-22

申请号：US17975092

申请日：2022-10-27

申请人： GaN Systems Inc.

发明人： Ahmad MIZAN ,  Edward MACROBBIE

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

摘要： A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

公开(公告)号：US11677396B2

公开(公告)日：2023-06-13

申请号：US17123316

申请日：2020-12-16

申请人： GaN Systems Inc.

发明人： Juncheng Lu ,  Larry Spaziani

IPC分类号： H03K17/687 ,  H03K17/567

CPC分类号： H03K17/6871 ,  H03K17/567 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

摘要： Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

公开(公告)号：US11676899B2

公开(公告)日：2023-06-13

申请号：US17061839

申请日：2020-10-02

申请人： GaN Systems Inc.

发明人： Thomas Macelwee

IPC分类号： H01L29/78 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L29/16 ,  H01L29/739

CPC分类号： H01L23/5329 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/1608 ,  H01L29/7393 ,  H01L29/78

摘要： Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.