公开(公告)号：US20130153969A1

公开(公告)日：2013-06-20

申请号：US13419156

申请日：2012-03-13

申请人： Ying-Zong JUANG ,  Hann-Huei Tsai ,  Hsin-Hao Liao ,  Chen-Fu Lin

发明人： Ying-Zong JUANG ,  Hann-Huei Tsai ,  Hsin-Hao Liao ,  Chen-Fu Lin

IPC分类号： H01L29/66

CPC分类号： G01N27/4145

摘要： A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor.

摘要翻译： 提供了一种用于金属氧化物半导体场效应晶体管（MOSFET）传感器的结构。 该结构包括MOSFET，感测膜和参考电极。 参考电极和感测膜形成在MOSFET的第一表面上并且被布置成使得参考电极和感测膜彼此均匀且电耦合。 因此，感测膜和参考电极之间的电场均匀地分布在其间，以稳定MOSFET传感器的工作信号。

公开(公告)号：US08219879B2

公开(公告)日：2012-07-10

申请号：US12707848

申请日：2010-02-18

申请人： Chien-Ming Wu ,  Ming-Der Shieh ,  Chun-Ming Huang ,  Chi-Sheng Lin ,  Shih-Hao Fang ,  Shing-Chung Tang

发明人： Chien-Ming Wu ,  Ming-Der Shieh ,  Chun-Ming Huang ,  Chi-Sheng Lin ,  Shih-Hao Fang ,  Shing-Chung Tang

IPC分类号： H03M13/00 ,  G11C29/00 ,  G06F11/00

CPC分类号： H03M13/116 ,  H03M13/1137 ,  H03M13/6505 ,  H03M13/6566

摘要： A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

摘要翻译： 提供了一种用于使用相同方法来布置低复杂度低密度奇偶校验（LDPC）解码器和低复杂度LDPC解码器的存储器的方法。 用于布置低复杂度LDPC解码器的存储器的方法的主要思想是将至少一个或两个小容量存储器块合并到一个存储器组中，使得存储器区域可以减少，读取或写入中的功耗 数据降低。 此外，由于合并的存储器组在读取或写入数据时共享相同的地址线，所以使用至少一个延迟单元来调整读取或写入顺序，从而确保数据的有效性。 使用所公开的方法的低复杂度LDPC解码器可以满足高处理速率和低功耗的需求。

公开(公告)号：US20110133256A1

公开(公告)日：2011-06-09

申请号：US12708546

申请日：2010-02-19

申请人： Chin-Fong Chiu ,  Ying Zong Juang ,  Hann Huei Tsai ,  Sheng-Hsiang Tseng ,  Chen-Fu Lin

发明人： Chin-Fong Chiu ,  Ying Zong Juang ,  Hann Huei Tsai ,  Sheng-Hsiang Tseng ,  Chen-Fu Lin

IPC分类号： H01L29/84

CPC分类号： B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81C2203/0714 ,  B81C2203/0735 ,  G01F1/28 ,  H01L27/0617

摘要： The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.

摘要翻译： 本发明公开了一种CMOS-MEMS悬臂结构。 CMOS-MEMS悬臂结构包括基板，电路结构和悬臂梁。 基板具有限定在其上的电路区域和传感器单元区域。 电路结构形成在电路区域中。 悬臂梁设置在传感器单元区域中，其一端浮在基板上方，另一端连接到电路结构。 通过上述结构，可以简化本发明的CMOS-MEMS悬臂结构的制造工艺。 此外，悬臂梁的结构变薄，因此具有较高的灵敏度。

公开(公告)号：US20100059886A1

公开(公告)日：2010-03-11

申请号：US12292261

申请日：2008-11-14

申请人： Chin-Long Wey ,  Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyan Yang ,  Wei-De Chien

发明人： Chin-Long Wey ,  Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyan Yang ,  Wei-De Chien

IPC分类号： H01L23/48

CPC分类号： H01L25/0655 ,  H01L23/3121 ,  H01L23/538 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/48 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention discloses a carrier structure of a System-on-Chip (SoC) with a custom interface. The carrier structure includes a substrate, at least one common die, at least one custom interface and a molding compound. The common die and the custom interface are disposed on the substrate. The molding compound is used to package the common die which electrically connects to the substrate and the custom interface respectively. The carrier structure which includes the common die can form a complete SoC by connecting to an expansive die through the custom interface. The carrier structure with the common die which can be tested and certified in advance allows reducing and simplifying the developing procedures of the SoC.

公开(公告)号：US07571414B2

公开(公告)日：2009-08-04

申请号：US11453103

申请日：2006-06-15

申请人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

发明人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/66

摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

摘要翻译： 通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统 因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。 此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程 从而得出。

公开(公告)号：US08466521B2

公开(公告)日：2013-06-18

申请号：US12724435

申请日：2010-03-16

申请人： Chin-Long Wey ,  Chin-Fong Chiu ,  Ying-Zong Juang ,  Hann-Huei Tsai ,  Chen-Fu Lin

发明人： Chin-Long Wey ,  Chin-Fong Chiu ,  Ying-Zong Juang ,  Hann-Huei Tsai ,  Chen-Fu Lin

IPC分类号： H01L31/119

CPC分类号： H01L29/78 ,  G01N27/414 ,  H01L29/4958

摘要： A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.

摘要翻译： 提供氢离子敏感场效应晶体管及其制造方法。 氢离子敏感场效应晶体管包括半导体衬底，绝缘层，晶体管栅极和感测膜。 在具有源极区域和漏极区域的半导体衬底上限定栅极区域。 绝缘层形成在半导体衬底上的栅极区域内。 晶体管栅极沉积在栅极区内并且包括第一栅极层。 此外，第一栅极层是铝层，并且在其上限定感测窗口。 感测膜是通过氧化第一栅极层而在感测窗内形成的氧化铝膜。 因此，在没有任何膜沉积工艺的情况下形成感测膜，因此简化了制造方法。

公开(公告)号：US20120102254A1

公开(公告)日：2012-04-26

申请号：US12961783

申请日：2010-12-07

申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Hui-Ming Lin ,  Chien-Ming Wu ,  Kai-Chao Yang ,  Yu-Tsang Chang

发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Hui-Ming Lin ,  Chien-Ming Wu ,  Kai-Chao Yang ,  Yu-Tsang Chang

IPC分类号： G06F13/20

CPC分类号： G06F13/385 ,  G06F2213/0058

摘要： The present invention discloses a virtualized peripheral hardware platform system. The virtualized peripheral hardware platform system includes a first hardware platform and a software platform, which is executed in a second hardware platform. The first hardware platform is in signal communication with the second hardware platform. The software platform not only simulates the operation of the peripheral device of the first hardware platform but also simulates input signals of virtual peripheral devices and then transmits the input signals to the first hardware platform to conduct further calculations. Furthermore, the input/output (I/O) interface of the second hardware platform can be simulated as the I/O interface of the first hardware platform, so as to decrease the number of the I/O interface which the first hardware platform needed and downsize the first hardware platform.

摘要翻译： 本发明公开了一种虚拟化的外围硬件平台系统。 虚拟化外设硬件平台系统包括第一个硬件平台和一个在第二个硬件平台上执行的软件平台。 第一个硬件平台与第二个硬件平台进行信号通信。 该软件平台不仅模拟第一硬件平台的外围设备的运行，而且模拟虚拟外围设备的输入信号，然后将输入信号发送到第一硬件平台进行进一步的计算。 此外，可以将第二硬件平台的输入/输出（I / O）接口模拟为第一硬件平台的I / O接口，从而减少第一硬件平台所需的I / O接口数量 并缩小了第一个硬件平台。

公开(公告)号：US20110169056A1

公开(公告)日：2011-07-14

申请号：US12724435

申请日：2010-03-16

申请人： Chin-Long Wey ,  Chin-Fong Chiu ,  Ying-Zong Juang ,  Hann-Huei Tsai ,  Chen-Fu Lin

发明人： Chin-Long Wey ,  Chin-Fong Chiu ,  Ying-Zong Juang ,  Hann-Huei Tsai ,  Chen-Fu Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  G01N27/414 ,  H01L29/4958

摘要： A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.

摘要翻译： 提供氢离子敏感场效应晶体管及其制造方法。 氢离子敏感场效应晶体管包括半导体衬底，绝缘层，晶体管栅极和感测膜。 在具有源极区域和漏极区域的半导体衬底上限定栅极区域。 绝缘层形成在半导体衬底上的栅极区域内。 晶体管栅极沉积在栅极区内并且包括第一栅极层。 此外，第一栅极层是铝层，并且在其上限定感测窗口。 感测膜是通过氧化第一栅极层而在感测窗内形成的氧化铝膜。 因此，在没有任何膜沉积工艺的情况下形成感测膜，因此简化了制造方法。

公开(公告)号：US20110138248A1

公开(公告)日：2011-06-09

申请号：US12707848

申请日：2010-02-18

申请人： Chien-Ming Wu ,  Ming-Der Shieh ,  Chun-Ming Huang ,  Chi-Sheng Lin ,  Shih-Hao Fang ,  Shing-Chung Tang

发明人： Chien-Ming Wu ,  Ming-Der Shieh ,  Chun-Ming Huang ,  Chi-Sheng Lin ,  Shih-Hao Fang ,  Shing-Chung Tang

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1137 ,  H03M13/6505 ,  H03M13/6566

摘要： A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

摘要翻译： 提供了一种用于使用相同方法来布置低复杂度低密度奇偶校验（LDPC）解码器和低复杂度LDPC解码器的存储器的方法。 用于布置低复杂度LDPC解码器的存储器的方法的主要思想是将至少一个或两个小容量存储器块合并到一个存储器组中，使得存储器区域可以减少，读取或写入中的功耗 数据降低。 此外，由于合并的存储器组在读取或写入数据时共享相同的地址线，所以使用至少一个延迟单元来调整读取或写入顺序，从而确保数据的有效性。 使用所公开的方法的低复杂度LDPC解码器可以满足高处理速率和低功耗的需求。

公开(公告)号：US20100277203A1

公开(公告)日：2010-11-04

申请号：US12489624

申请日：2009-06-23

申请人： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

发明人： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

IPC分类号： H03K5/19

CPC分类号： H03K5/19 ,  H03K5/1534 ,  H03L7/0891 ,  H03L7/10

摘要： An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

摘要翻译： 边缘丢失检测器结构包括第一检测器，第一延迟单元，第一逻辑门，第二检测器，第二延迟单元和第二逻辑门。 在分别输入到边缘丢失检测器结构中之后，第一和第二检测器检测第一参考信号和第一时钟信号，然后分别由第一和第二逻辑门进行循环抑制，以产生 第二参考信号和呈现小于2＆pgr的相位差的第二时钟信号。 此外，边缘丢失检测器结构产生对应于循环抑制的出现次数的补偿电流。 因此，使用边缘丢失检测器结构的锁相环（PLL）可以避免周期滑移问题并实现锁相的快速采集。