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111 条记录 (耗时 0.03 秒)

    Current constricting phase change memory element structure
    1.
    发明授权
    Current constricting phase change memory element structure 有权
    电流限制相变存储元件结构

    公开(公告)号：US07932507B2

    公开(公告)日：2011-04-26

    申请号：US12727672

    申请日：2010-03-19

    申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    IPC分类号： H01L29/02

    CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

    摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

    Method and circuit for transmitting a memory clock signal
    2.
    发明授权
    Method and circuit for transmitting a memory clock signal 有权
    用于发送存储器时钟信号的方法和电路

    公开(公告)号：US07886122B2

    公开(公告)日：2011-02-08

    申请号：US11466312

    申请日：2006-08-22

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G06F12/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/225 ,  G11C2207/107

    摘要： Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.

    摘要翻译： 本发明的实施例通常提供用于发送和接收时钟信号的方法和装置。 在一个实施例中，该方法包括在存储器件处接收第一时钟信号和第二时钟信号。 第一时钟信号的频率可以小于第二时钟信号的频率。 该方法还包括使用第二时钟信号执行两个或多个数据访问操作。 两个或多个数据访问操作之一可以包括读取操作，并且两个或多个数据访问操作中的一个可以包括写入操作。 该方法还包括使用第一时钟信号执行命令处理操作。

    Integrated circuit that stores first and second defective memory cell addresses
    4.
    发明授权
    Integrated circuit that stores first and second defective memory cell addresses 有权
    存储第一和第二有缺陷的存储单元地址的集成电路

    公开(公告)号：US07773438B2

    公开(公告)日：2010-08-10

    申请号：US12134485

    申请日：2008-06-06

    申请人： Khaled Fekih-Romdhane

    发明人： Khaled Fekih-Romdhane

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/789 ,  G11C2029/1208

    摘要： An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses and stores second addresses of the second defective memory cells in the volatile storage and in the non-volatile storage.

    摘要翻译： 一种包括存储单元阵列，易失性存储器，非易失性存储器和电路的集成电路。 电路被配置为从非易失性存储器检测第一缺陷存储器单元的第一地址以获得有意义的第一地址。 该电路经由感测第一地址检测第二个有缺陷的存储器单元，并将第二个有缺陷的存储器单元的第二个地址存储在易失性存储器和非易失性存储器中。

    INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST
    5.
    发明申请
    INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST 有权
    具有执行保持测试的控制电路的集成电路

    公开(公告)号：US20100091595A1

    公开(公告)日：2010-04-15

    申请号：US12251010

    申请日：2008-10-14

    申请人： Khaled Fekih-Romdhane

    发明人： Khaled Fekih-Romdhane

    IPC分类号： G11C29/00 ,  G11C8/18

    CPC分类号： G11C29/50 ,  G11C8/18 ,  G11C11/401 ,  G11C29/028 ,  G11C29/50016

    摘要： An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.

    摘要翻译： 集成电路包括存储器单元阵列，被配置为产生时钟信号的时钟发生器和被配置为基于时钟信号对存储器单元阵列执行保持测试的控制电路。 时钟信号的周期定义了保留测试的保留期。

    Sense amplifier biasing method and apparatus
    7.
    发明授权
    Sense amplifier biasing method and apparatus 失效
    感应放大器偏置方式和装置

    公开(公告)号：US07684273B2

    公开(公告)日：2010-03-23

    申请号：US11939903

    申请日：2007-11-14

    申请人： Hoon Ryu

    发明人： Hoon Ryu

    IPC分类号： G11C7/02

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/1048 ,  G11C11/4091 ,  G11C2207/065

    摘要： A memory device includes sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier circuitry. The current sink is operable to sink a bias current. The resistive element couples the current sink to the sense amplifier circuitry. The bias voltage applied to the sense amplifier circuitry corresponds to the voltage drop across the resistive element and current sink as induced by the bias current.

    摘要翻译： 存储器件包括读出放大器电路，电流吸收器和电阻元件。 感测放大器电路可操作以响应于施加到感测放大器电路的偏置电压来评估从包括在存储器件中的存储器阵列读取的数据。 电流吸收器可操作以吸收偏置电流。 电阻元件将电流吸收器耦合到读出放大器电路。 施加到感测放大器电路的偏置电压对应于由偏置电流引起的电阻元件和电流吸收器两端的电压降。

    Integrated circuit having a phase change memory cell including a narrow active region width
    9.
    发明授权
    Integrated circuit having a phase change memory cell including a narrow active region width 失效
    具有包括窄有源区宽度的相变存储单元的集成电路

    公开(公告)号：US07663909B2

    公开(公告)日：2010-02-16

    申请号：US11483873

    申请日：2006-07-10

    申请人： Jan Boris Philipp ,  Thomas Happ

    发明人： Jan Boris Philipp ,  Thomas Happ

    IPC分类号： G11C11/00

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

    摘要： A memory cell includes a first electrode and an opposing second electrode, and a memory stack between the first and second electrodes. The memory stack includes a first layer of thermal isolation material contacting the first electrode, a second layer of thermal isolation material contacting the second electrode, and a phase change material between the first layer of thermal isolation material and the second layer of thermal isolation material. In this regard, the phase change material defines an active region width that is less than a width of either of the first layer of thermal isolation material and the second layer of thermal isolation material.

    摘要翻译： 存储单元包括第一电极和相对的第二电极，以及在第一和第二电极之间的存储器堆叠。 存储器堆叠包括接触第一电极的第一层隔热材料，与第二电极接触的第二层热隔离材料，以及第一层热隔离材料层与第二层热隔离材料之间的相变材料。 在这方面，相变材料限定有效区宽度小于热隔离材料第一层和第二隔热层之一的宽度。

    Memory including two access devices per phase change element
    10.
    发明授权
    Memory including two access devices per phase change element 有权
    每个相变元件包含两个存取设备的存储器

    公开(公告)号：US07652914B2

    公开(公告)日：2010-01-26

    申请号：US11651157

    申请日：2007-01-09

    申请人： Thomas Nirschl ,  Roger Cheek ,  Mark Lamorey ,  Ming-Hsiu Lee

    发明人： Thomas Nirschl ,  Roger Cheek ,  Mark Lamorey ,  Ming-Hsiu Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/79

    摘要： A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.

    摘要翻译： 存储器包括位线和相变元件。 相变元件的第一侧耦合到位线。 存储器包括耦合到相变元件的第二侧的第一存取装置和耦合到相变元件的第二侧的第二存取装置。 存储器包括用于对位线进行预充电的电路和仅选择第一存取装置以将相变元件编程为第一状态的电路，并且选择第一存取装置和第二存取装置以将相变元件编程为第二 州。