公开(公告)号：US6101257A

公开(公告)日：2000-08-08

申请号：US900930

申请日：1997-07-25

申请人： Jurgen Lubbe ,  Peter Kirchlechner ,  Jorg Schambacher

发明人： Jurgen Lubbe ,  Peter Kirchlechner ,  Jorg Schambacher

IPC分类号： H04B1/08 ,  H03G5/00

CPC分类号： H04B1/082

摘要： An audio signal processor is disclosed which has at least one audio signal input and at least one audio signal output as well as at least one control input, and an audio signal processing unit connected between audio signal input and audio signal output, the audio signal processing unit having a programmable indicator tone generator circuit to be driven via the control input and whose indicator tone signal is switched to the audio signal output in accordance with the state of the control input.

摘要翻译： 公开了一种音频信号处理器，其具有至少一个音频信号输入和至少一个音频信号输出以及至少一个控制输入，以及连接在音频信号输入和音频信号输出之间的音频信号处理单元，音频信号处理 单元具有可编程的指示符乐音发生器电路，经由控制输入驱动，并且根据控制输入的状态将其指示音信号切换到音频信号输出。

公开(公告)号：US5955919A

公开(公告)日：1999-09-21

申请号：US900426

申请日：1997-07-25

申请人： Jurgen Lubbe ,  Peter Kirchlechner ,  Jorg Schambacher

发明人： Jurgen Lubbe ,  Peter Kirchlechner ,  Jorg Schambacher

IPC分类号： H03G1/00 ,  H03G3/12

CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03G1/0088 ,  H03F2203/45534

摘要： An electric signal processing circuit with an operational amplifier having a signal input, a feedback input and a signal output, and a nonlinear circuit device having a characteristic with a distortion-producing nonlinearity and located in the input signal circuit or in the feedback circuit of the operational amplifier, wherein a compensating circuit device having a characteristic with generally the same nonlinearity as the characteristic of the nonlinear circuit device is disposed in the feedback circuit or in the input signal circuit of the operational amplifier for compensating the distortion of the nonlinear circuit device.

摘要翻译： 具有具有信号输入，反馈输入和信号输出的运算放大器的电信号处理电路和具有失真产生非线性的特性的非线性电路装置，位于输入信号电路或反馈电路的反馈电路中 运算放大器，其中具有与非线性电路装置的特性大致相同的非线性的特性的补偿电路装置设置在用于补偿非线性电路装置的失真的运算放大器的反馈电路或输入信号电路中。

公开(公告)号：US5789968A

公开(公告)日：1998-08-04

申请号：US615736

申请日：1996-03-13

申请人： Udo John

发明人： Udo John

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/78 ,  H03K17/082 ,  H03K17/687

CPC分类号： H03K17/0822 ,  H03K17/6874

摘要： An integrated semiconductor circuit comprising an output terminal connected to a ground terminal via a series connection of a first switching transistor and a second switching transistor of inverse polarization with respect to the latter, each of said switching transistors having parasitic transistors. Whether the second semiconductor switch means is conducting or not, is dependent on the current flow through a resistor connected between gate and source of the second semiconductor switch means. Whether current flows through this resistor, is dependent on the switching condition of a further switching transistor, which in turn is also determined by the output signal of a comparator circuit by means of which a potential corresponding to the potential present at output terminal is compared to a reference potential.

摘要翻译： 一种集成半导体电路，包括通过第一开关晶体管和逆极化的第二开关晶体管的串联连接到接地端子的输出端子，每个所述开关晶体管具有寄生晶体管。 第二半导体开关装置是否导通，取决于连接在第二半导体开关装置的栅极和源极之间的电阻器的电流。 电流是否流经该电阻，取决于另一个开关晶体管的开关状态，而另一个开关晶体管又由比较器电路的输出信号决定，通过该比较器将与输出端存在的电位相对应的电位与 参考潜力。

公开(公告)号：US5739705A

公开(公告)日：1998-04-14

申请号：US746768

申请日：1996-11-15

申请人： Udo John

发明人： Udo John

IPC分类号： G05F3/26 ,  H03K5/153 ,  H03K3/037

CPC分类号： G05F3/267

摘要： A hysteresis comparator circuit using, for a virtually power-free detection of the voltage value to be subjected to a comparison, a differential stage utilizing on one end load transistors and on the other hand a negative feedback stage and preferably a current mirror stage. The control electrode of one load transistor is fed with the voltage to be used for the comparison. The control electrode of the other load transistor is fed with a reference voltage on the basis of which this load transistor forms a constant load impedance. The second load transistor has a third load transistor connected in parallel thereto, which in response to the output signal of the comparator is either conducting or blocking, so that in accordance with the output signal of the comparator, an additional load impedance is connected in parallel to the impedance of the second load transistor or no such connection is made.

摘要翻译： 一种迟滞比较器电路，用于对要进行比较的电压值的实际无功率检测，在一端负载晶体管上使用差分级，另一方面使用负反馈级，优选地为电流镜级。 一个负载晶体管的控制电极被馈送用于比较的电压。 另一个负载晶体管的控制电极被馈送参考电压，在此基础上该负载晶体管形成恒定的负载阻抗。 第二负载晶体管具有并联连接的第三负载晶体管，其响应于比较器的输出信号导通或阻塞，使得根据比较器的输出信号，附加负载阻抗并联 到第二负载晶体管的阻抗，或者不进行这种连接。

公开(公告)号：US5726992A

公开(公告)日：1998-03-10

申请号：US569781

申请日：1995-12-08

申请人： Gerhard Roither

发明人： Gerhard Roither

IPC分类号： H04L27/18 ,  H04B17/00 ,  H04H40/45 ,  H04L7/033 ,  H04L25/49 ,  H03M13/00

CPC分类号： H04H20/02 ,  H04H40/45 ,  H04H2201/13 ,  H04L7/0331

摘要： A method of assessing the quality and/or existence of a biphase-modulated digital RDS signal in a radio signal broadcast by a radio transmitter and received by a radio receiver equipped for RDS, in which a bit rate clock signal is produced on the receiver side whose bit rate is identical to that of the RDS signal, the bits both of the RDS signal and of the bit rate clock signal are each composed of two half bits, and of the two RDS half bits belonging to an RDS bit, one has a positive phase and the other one has a negative phase, and in which, for quality or existence assessment, the number of positive phase signs and the number of negative phase signs are determined which are each contained in the RDS signal during the half bit periods of a predetermined number of n adjacent half bits of the bit rate clock signal, and the RDS signal, depending on whether or not the ratio between the number of positive phase signs ascertained and the number of negative phase signs ascertained corresponds to a predetermined numerical ratio, is rated as being a signal of good quality or as a signal of poor quality, respectively, and in which an odd integer is used for n, which is greater than 2, and preferably is 3.

摘要翻译： 一种在由无线电发射机广播的无线电信号中评估双相调制数字RDS信号的质量和/或存在的方法，所述无线电信号由配备有RDS的无线电接收机接收，其中在接收机侧产生比特率时钟信号 其比特率与RDS信号的比特率相同，RDS信号和比特率时钟信号的比特分别由两个半位组成，并且属于RDS位的两个RDS半位中的一个具有 正相，另一个具有负相位，并且其中，对于质量或存在评估，确定正相位符号的数量和负相位符号的数量，其中每个包含在RDS信号的半位周期期间 比特率时钟信号的预定数量的n个相邻的半位和RDS信号，这取决于确定的正相位符号数与确定的相位符号数之间的比率 分别被认为是质量好的信号或质量差的信号，并且其中使用奇数整数n大于2，优选为3。

公开(公告)号：US5592416A

公开(公告)日：1997-01-07

申请号：US358000

申请日：1994-12-15

申请人： Rainer Bonitz ,  Peter Birkenseher

发明人： Rainer Bonitz ,  Peter Birkenseher

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C29/00 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  H03K19/177 ,  G11C11/34

CPC分类号： G11C16/0441 ,  G11C29/50 ,  G11C16/04

摘要： An electronic storage circuit for storing information, in particular switch control information for alternately switching circuit parts of integrated monolithic circuits, having two series connections inserted between the two poles of a voltage supply source each including an EPROM transistor and a MOS transistor, the control gates of the two EPROM transistors being connected jointly with a reference voltage source, and the gates of the two MOS transistors with the connection point of the EPROM transistor and the MOS transistor of the other series connection.

摘要翻译： 一种用于存储信息的电子存储电路，特别是用于交替地切换集成单片电路的电路部分的开关控制信息，其具有插入在包括EPROM晶体管和MOS晶体管的电压源的两极之间的两个串联连接，所述控制栅极 两个EPROM晶体管与参考电压源连接，两个MOS晶体管的栅极与EPROM晶体管的连接点和另一个串联的MOS晶体管连接。

公开(公告)号：US4890012A

公开(公告)日：1989-12-26

申请号：US199836

申请日：1988-05-27

申请人： Josef Stockinger

发明人： Josef Stockinger

IPC分类号： H03K17/16 ,  H03K17/687

CPC分类号： H03K17/162 ,  H03K17/6872

摘要： A switch means designed as an integrated circuit possesses two series-connected FETs (Q1P, Q2P; Q1N, Q2N) whose common switching point (N5, N6) is clamped via a clamp FET (Q3N, Q3P) to a reference potential. The conductivity type of the clamp FET (Q3N, Q3P) is opposite the conductivity type of the two series-connected FETs (Q1P, Q2P; Q1N, Q2N). In the case of an n-channel clamp FET (Q3N), the latter is connected to negative potential. In the case of a p-channel clamp FET (Q3P), it is connected to positive potential.

摘要翻译： 设计为集成电路的开关装置具有两个串联连接的FET（Q1P，Q2P; Q1N，Q2N），其公共开关点（N5，N6）通过钳位FET（Q3N，Q3P）钳位到参考电位。 钳位FET（Q3N，Q3P）的导电类型与两个串联连接的FET（Q1P，Q2P; Q1N，Q2N）的导电类型相反。 在n沟道钳位FET（Q3N）的情况下，后者连接到负电位。 在p沟道钳位FET（Q3P）的情况下，它连接到正电位。

公开(公告)号：US5689199A

公开(公告)日：1997-11-18

申请号：US518765

申请日：1995-08-24

申请人： Ricardo Erckert

发明人： Ricardo Erckert

IPC分类号： H03K3/2897 ,  H03F3/345 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K5/08 ,  H03K5/24 ,  H03K17/30 ,  H03K5/153 ,  H03K3/037

CPC分类号： H03K5/2418 ,  H03F3/345 ,  H03K17/30 ,  H03K3/0231

摘要： A comparator with hysteresis in bipolar technology having a voltage/current converter with a voltage input forming the comparator input connection, and a current output, a bistable current source with a current feeding connection coupled with the current output of the voltage/current converter and a current output connection forming the comparator output, the bistable current source being currentless in a first stable state and consuming current only in the second stable state, the firing current which must be fed to the current feeding connection to switch the bistable current source from the currentless state to the power-consuming state being different from the quenching current which must be fed to the current feeding connection to switch the bistable current source from the power-consuming state to the currentless state, to obtain a hysteresis of the comparator, and all transistors being formed as bipolar transistors. The entire power consumption of such a comparator can be made extremely low in one of its two switching positions.

摘要翻译： 具有双极性技术中具有迟滞的比较器具有具有形成比较器输入连接的电压输入的电压/电流转换器和电流输出，具有与电压/电流转换器的电流输出耦合的电流馈送连接的双稳态电流源和 电流输出连接形成比较器输出，双稳态电流源无电流处于第一稳定状态，并且仅在第二稳定状态下消耗电流，该点火电流必须馈送到电流馈电连接以将双稳态电流源从无电流 状态到功耗状态不同于必须馈送到电流馈电连接以将双稳态电流源从功耗状态切换到无电流状态的淬灭电流，以获得比较器的滞后，并且所有晶体管 被形成为双极晶体管。 这种比较器的整个功耗在其两个开关位置中的一个中可以非常低。

公开(公告)号：US5559416A

公开(公告)日：1996-09-24

申请号：US335809

申请日：1995-01-31

申请人： Petr Hrassky

发明人： Petr Hrassky

IPC分类号： H02P7/06 ,  H02P7/03 ,  G05B9/02 ,  H03F3/45

CPC分类号： H02P7/04

摘要： A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V.sub.S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator.

摘要翻译： PCT No.PCT / EP93 / 01212 Sec。 371日期1995年1月31日 102（e）日期1995年1月31日PCT提交1993年5月14日PCT公布。 公开号WO93 / 23920 PCT 日期：1993年11月25日一种控制电路，特别是用于定位系统中的直流控制，包括差分电路（1），控制逻辑（2）和连接在电源电压VS和参考电压之间的全桥（3） 电位GND。 差分电路（1）具有第一滞后比较器（HC1）和第二滞后比较器（HC2）。 两个迟滞比较器（HC1，HC2）的两个比较器输入（HC1-，HC1 +，HC2-，HC2 +）分别连接到控制电路的两个输入端（IN1，IN2）中的一个，并与 各个其他比较器（HC1，HC2）。 每个比较器（HC1，HC2）的反相输入端连接到相应的其它比较器的同相输入端。

公开(公告)号：US5376891A

公开(公告)日：1994-12-27

申请号：US967635

申请日：1992-10-28

申请人： Peter Kirchlechner

发明人： Peter Kirchlechner

IPC分类号： H03D3/02 ,  H03D1/22 ,  H03H19/00 ,  H03L7/085 ,  H03L7/093 ,  H01D3/02

CPC分类号： H03D1/22

摘要： A circuit combining the functions of phase-sensitive rectifier and integrator uses an operational amplifier and capacitors. A control signal switches a capacitor in and out of a feedback loop containing a second feedback capacitor, resulting in a residual charge in the second feedback capacitor if there is a phase-difference between an input signal and the control signal. The invention may also incorporate an automatic offset compensation circuit by using additional switches and a second control signal. The capacitor that is switched in and out of the feedback loop is coupled to a compensation capacitor during periods when the capacitor is not being used for the phase-sensitive rectifier and integrator portions of the circuit. The circuit arrangement allows the use of long time constants in the integrator portion of the circuit.

摘要翻译： 结合相敏整流器和积分器功能的电路使用运算放大器和电容器。 控制信号将包含第二反馈电容器的反馈回路中的电容器切换到外部，从而在输入信号和控制信号之间存在相位差时导致第二反馈电容器中的残余电荷。 本发明还可以通过使用附加开关和第二控制信号来结合自动偏移补偿电路。 在电容器不用于电路的相敏整流器和积分器部分的时段期间，接入和退出反馈回路的电容器耦合到补偿电容器。 电路布置允许在电路的积分器部分中使用长时间常数。