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公开(公告)号：US20230377999A1
公开(公告)日：2023-11-23
申请号：US17746450
申请日：2022-05-17
Inventor： Szu-Ying CHEN , Chia-Cheng CHEN , Liang-Yin CHEN , Sen-Hong SYUE
IPC: H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/311 , H01L21/3115 , H01L29/66
CPC classification number: H01L21/823878 , H01L27/092 , H01L29/0665 , H01L29/42392 , H01L29/78696 , H01L21/0259 , H01L21/31111 , H01L21/31155 , H01L21/823807 , H01L29/66742
Abstract: A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.
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公开(公告)号：US20240363404A1
公开(公告)日：2024-10-31
申请号：US18767722
申请日：2024-07-09
Inventor： Chia-Cheng CHEN , Tang-Kuei CHANG , Yee-Chia YEO , Huicheng CHANG , Wei-Wei LIANG , Ji CUI , Fu-Ming HUANG , Kei-Wei CHEN , Liang-Yin CHEN
IPC: H01L21/768 , H01L21/321 , H01L23/522 , H01L23/532 , H01L23/535 , H01L29/08 , H01L29/45 , H01L29/78
CPC classification number: H01L21/76859 , H01L21/3212 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53238 , H01L23/535 , H01L29/0847 , H01L29/45 , H01L29/7851
Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.
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公开(公告)号：US20230230976A1
公开(公告)日：2023-07-20
申请号：US18186405
申请日：2023-03-20
Inventor： Chia-Cheng CHEN , Chia-Ling CHAN , Liang-Yin CHEN , Huicheng CHANG
IPC: H01L27/088 , H01L29/06 , H01L21/8234 , H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/78
CPC classification number: H01L27/0886 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L27/0924 , H01L29/0649 , H01L29/785 , H01L29/66545 , H01L27/1211
Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes a gate spacer on a sidewall of the gate structure. The semiconductor structure also includes a source/drain feature adjacent to the gate structure. The semiconductor structure also includes a doped region extending along a bottom surface of the gate spacer. The source/drain feature has a curved sidewall connecting a top surface of the doped region and a bottom surface of the doped region.
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公开(公告)号：US20250044708A1
公开(公告)日：2025-02-06
申请号：US18920346
申请日：2024-10-18
Inventor： Ru-Gun LIU , Huicheng CHANG , Chia-Cheng CHEN , Jyu-Horng SHIEH , Liang-Yin CHEN , Shu-Huei SUEN , Wei-Liang LIN , Ya Hui CHANG , Yi-Nien SU , Yung-Sung YEN , Chia-Fong CHANG , Ya-Wen YEH , Yu-Tien SHEN
Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
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公开(公告)号：US20240379663A1
公开(公告)日：2024-11-14
申请号：US18314555
申请日：2023-05-09
Inventor： Yu-Chang LIN , Liang-Yin CHEN , Huicheng CHANG , Yee-Chia YEO
IPC: H01L27/088 , H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: An integrated circuit includes a substrate, a well formed over a portion of the substrate, a stacked structure formed over a first portion of the well, a doped epi structure formed over a second portion of the well adjacent the stacked structure and below a plane defined by an upper surface of the first portion of the well, and a source/drain region formed over the doped epi structure.
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Patent Agency Ranking
公开(公告)号：US20240047209A1
公开(公告)日：2024-02-08
申请号：US18488979
申请日：2023-10-17
Inventor： Yu-Tien SHEN , Chih-Kai YANG , Hsiang-Ming CHANG , Chun-Yen CHANG , Ya-Hui CHANG , Wei-Ting CHIEN , Chia-Cheng CHEN , Liang-Yin CHEN
IPC: H01L21/027 , H01L21/02 , H01L29/66 , H01L21/3213 , H01L21/28
CPC classification number: H01L21/0274 , H01L21/02359 , H01L29/66545 , H01L21/32133 , H01L21/32139 , H01L21/28088
Abstract: A method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.
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公开(公告)号：US20240006247A1
公开(公告)日：2024-01-04
申请号：US17854997
申请日：2022-06-30
Inventor： Bau-Ming WANG , Liang-Yin CHEN , Huicheng CHANG , Yee-Chia YEO
IPC: H01L21/8238 , H01L21/265
CPC classification number: H01L21/823892 , H01L21/2652
Abstract: A method for manufacturing a semiconductor device includes: forming a first type well in a substrate; and after forming the first type well in the substrate, forming a second type well in the substrate, where the second type well has a conductivity type different from that of the first type well. One of the first and second type wells is formed by sequentially performing multiple ion implantations that use different energies, and one of the ion implantations that uses a lowest energy among the ion implantations is performed first among the ion implantations.
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公开(公告)号：US20230093608A1
公开(公告)日：2023-03-23
申请号：US17994153
申请日：2022-11-25
Inventor： Tung-Po HSIEH , Su-Hao LIU , Hong-Chih LIU , Jing-Huei HUANG , Jie-Huang HUANG , Lun-Kuang TAN , Huicheng CHANG , Liang-Yin CHEN , Kuo-Ju CHEN
IPC: H01L21/768 , H01L29/66 , H01L29/78 , H01L23/532 , H01L21/8234 , H01L23/522 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L29/417
Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.
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公开(公告)号：US20240395550A1
公开(公告)日：2024-11-28
申请号：US18789485
申请日：2024-07-30
Inventor： Yu-Tien SHEN , Chih-Kai YANG , Hsiang-Ming CHANG , Chun-Yen CHANG , Ya-Hui CHANG , Wei-Ting CHIEN , Chia-Cheng CHEN , Liang-Yin CHEN
IPC: H01L21/027 , H01L21/02 , H01L21/28 , H01L21/3213 , H01L29/66
Abstract: A method for fabricating a semiconductor device is provided. The method includes coating a photoresist film over a target layer over a semiconductor substrate; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer along a direction tilted with respect to a normal direction of the semiconductor substrate, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.
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公开(公告)号：US20230387316A1
公开(公告)日：2023-11-30
申请号：US17825516
申请日：2022-05-26
Inventor： Shuen-Shin LIANG , Min-Chiang CHUANG , Chia-Cheng CHEN , Chun-Hung WU , Liang-Yin CHEN , Sung-Li WANG , Pinyen LIN , Kuan-Kan HU , Jhih-Rong HUANG , Szu-Hsian LEE , Tsun-Jen CHAN , Cheng-Wei LIAN , Po-Chin CHANG , Chuan-Hui SHEN , Lin-Yu HUANG , Yuting CHENG , Yan-Ming TSAI , Hong-Mao LEE
IPC: H01L29/786 , H01L29/417
CPC classification number: H01L29/78651 , H01L29/41733
Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.
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